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公开(公告)号：US08806135B1
公开(公告)日：2014-08-12
申请号：US13250481
申请日：2011-09-30
IPC分类号： G06F12/08
CPC分类号： G06F9/30043 , G06F9/3826 , G06F9/3834
摘要： A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. When missed load instructions are reissued from the outstanding load miss buffer, data for the missed load instructions are read from the load miss result buffer rather than the level one cache. Because the data is stored in the load miss result buffer, other instructions that may change the data in level one cache do not cause data hazards with the missed load instructions.
摘要翻译： 具有未完成的负载未命中缓冲器和加载未命中结果缓冲器的加载/存储单元被配置为从具有一级缓存的存储器系统读取数据。 丢失的加载指令存储在未完成的负载丢失缓冲器中。 加载/存储单元使用单个高速缓存访问来检索多个相关的错过加载指令的数据，并将数据存储在加载未结果缓冲器中。 当错过的加载指令从未完成的负载丢失缓冲区重新发出时，从加载未命中结果缓冲区而不是一级缓存读取错误加载指令的数据。 由于数据存储在加载未命中结果缓冲区中，可能会更改一级缓存中的数据的其他指令不会导致丢失加载指令的数据危险。
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公开(公告)号：US08793435B1
公开(公告)日：2014-07-29
申请号：US13250596
申请日：2011-09-30
IPC分类号： G06F12/10
CPC分类号： G06F12/0897 , G06F9/3834 , G06F12/084 , G06F12/0855
摘要： A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single memory access and stores the data in the load miss result buffer. The load miss result buffer includes dependent data lines, dependent data selection circuits, shared data lines and shared data selection circuits. The dependent data selection circuits are configured to select a subset of data from the memory system for storing in an associated dependent data line. Similarly, the shared data selection circuits are configured to select a subset of data from the memory system for storing in an associated shared data line.
摘要翻译： 具有未完成的负载未命中缓冲器和加载未命中结果缓冲器的加载/存储单元被配置为从具有一级缓存的存储器系统读取数据。 丢失的加载指令存储在未完成的负载丢失缓冲器中。 加载/存储单元使用单个存储器访问检索多个相关的未完成加载指令的数据，并将数据存储在加载未结果缓冲器中。 加载未结结果缓冲器包括从属数据线，相关数据选择电路，共享数据线和共享数据选择电路。 依赖数据选择电路被配置为从存储器系统中选择数据的子集以存储在相关联的依赖数据线中。 类似地，共享数据选择电路被配置为从存储器系统中选择数据的子集以存储在相关联的共享数据线中。
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公开(公告)号：US09280479B1
公开(公告)日：2016-03-08
申请号：US13478100
申请日：2012-05-22
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F9/3824 , G06F12/0868 , G06F12/0897 , G06F2212/1024
摘要： A memory system having increased throughput is disclosed. Specifically, the memory system includes a first level write combining queue that reduces the number of data transfers between a level one cache and a level two cache. In addition, a second level write merging buffer can further reduce the number of data transfers within the memory system. The first level write combining queue receives data from the level one cache. The second level write merging buffer receives data from the first level write combining queue. The level two cache receives data from both the first level write combining queue and the second level write merging buffer. Specifically, the first level write combining queue combines multiple store transactions from the load store units to associated addresses. In addition, the second level write merging buffer merges data from the first level write combining queue.
摘要翻译： 公开了一种具有增加的吞吐量的存储器系统。 具体来说，存储器系统包括一级写入组合队列，其减少一级缓存和二级缓存之间的数据传输次数。 此外，第二级写入合并缓冲器可以进一步减少存储器系统内的数据传输的数量。 第一级写入组合队列从一级缓存接收数据。 第二级写合并缓冲区从第一级写入组合队列接收数据。 二级缓存从第一级写入组合队列和第二级写入合并缓冲区接收数据。 具体来说，第一级写入组合队列将来自加载存储单元的多个存储事务组合到相关联的地址。 另外，第二级写入合并缓冲区合并来自第一级写入组合队列的数据。
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公开(公告)号：US08850121B1
公开(公告)日：2014-09-30
申请号：US13250544
申请日：2011-09-30
IPC分类号： G06F12/08
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/34
摘要： A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. The outstanding load miss buffer stores a first missed load instruction in a first primary entry. Additional missed load instructions that are dependent on the first missed load instructions are stored in dependent entries of the first primary entry or in shared entries. If a shared entry is used for a missed load instruction the shared entry is associated with the primary entry.
摘要翻译： 具有未完成的负载未命中缓冲器和加载未命中结果缓冲器的加载/存储单元被配置为从具有一级缓存的存储器系统读取数据。 丢失的加载指令存储在未完成的负载丢失缓冲器中。 加载/存储单元使用单个高速缓存访问来检索多个相关的错过加载指令的数据，并将数据存储在加载未结果缓冲器中。 未完成的负载未命中缓冲存储器将第一个缺省加载指令存储在第一个初级条目中。 依赖于第一个错过的加载指令的附加的错过加载指令被存储在第一主入口的相关条目或共享条目中。 如果共享条目用于错过加载指令，则共享条目与主条目相关联。
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公开(公告)号：US08949581B1
公开(公告)日：2015-02-03
申请号：US13103833
申请日：2011-05-09
CPC分类号： G06F9/3834 , G06F9/3836 , G06F9/3842
摘要： A load scheduler capable of limited issuing of out of order load instruction is disclosed. The load scheduler uses a max skipping threshold which limits the number of skipping load instructions and a max skipped threshold which limits the number of skipped load instructions. An address tag for a skipping instruction is stored in a skipping load instruction tracking unit when a skipping load instruction is issued. When a skipped load instruction issues, the address tag of the skipped load instruction is compared to the address tag of the skipping instruction to determine if a hazard from the out of order issuing of the skipping load instruction caused a hazard and must be flushed.
摘要翻译： 公开了能够限制发出无序加载指令的负载调度器。 负载调度器使用限制跳过加载指令数量的最大跳过阈值和限制跳过加载指令数量的最大跳过阈值。 当发出跳过加载指令时，用于跳过指令的地址标签被存储在跳过加载指令跟踪单元中。 当跳过的加载指令发生时，将跳过的加载指令的地址标签与跳过指令的地址标签进行比较，以确定跳过加载指令的乱序发出的危险是否导致危险，并且必须被刷新。
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