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公开(公告)号：US08806135B1
公开(公告)日：2014-08-12
申请号：US13250481
申请日：2011-09-30
IPC分类号： G06F12/08
CPC分类号： G06F9/30043 , G06F9/3826 , G06F9/3834
摘要： A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. When missed load instructions are reissued from the outstanding load miss buffer, data for the missed load instructions are read from the load miss result buffer rather than the level one cache. Because the data is stored in the load miss result buffer, other instructions that may change the data in level one cache do not cause data hazards with the missed load instructions.
摘要翻译： 具有未完成的负载未命中缓冲器和加载未命中结果缓冲器的加载/存储单元被配置为从具有一级缓存的存储器系统读取数据。 丢失的加载指令存储在未完成的负载丢失缓冲器中。 加载/存储单元使用单个高速缓存访问来检索多个相关的错过加载指令的数据，并将数据存储在加载未结果缓冲器中。 当错过的加载指令从未完成的负载丢失缓冲区重新发出时，从加载未命中结果缓冲区而不是一级缓存读取错误加载指令的数据。 由于数据存储在加载未命中结果缓冲区中，可能会更改一级缓存中的数据的其他指令不会导致丢失加载指令的数据危险。
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公开(公告)号：US08793435B1
公开(公告)日：2014-07-29
申请号：US13250596
申请日：2011-09-30
IPC分类号： G06F12/10
CPC分类号： G06F12/0897 , G06F9/3834 , G06F12/084 , G06F12/0855
摘要： A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single memory access and stores the data in the load miss result buffer. The load miss result buffer includes dependent data lines, dependent data selection circuits, shared data lines and shared data selection circuits. The dependent data selection circuits are configured to select a subset of data from the memory system for storing in an associated dependent data line. Similarly, the shared data selection circuits are configured to select a subset of data from the memory system for storing in an associated shared data line.
摘要翻译： 具有未完成的负载未命中缓冲器和加载未命中结果缓冲器的加载/存储单元被配置为从具有一级缓存的存储器系统读取数据。 丢失的加载指令存储在未完成的负载丢失缓冲器中。 加载/存储单元使用单个存储器访问检索多个相关的未完成加载指令的数据，并将数据存储在加载未结果缓冲器中。 加载未结结果缓冲器包括从属数据线，相关数据选择电路，共享数据线和共享数据选择电路。 依赖数据选择电路被配置为从存储器系统中选择数据的子集以存储在相关联的依赖数据线中。 类似地，共享数据选择电路被配置为从存储器系统中选择数据的子集以存储在相关联的共享数据线中。
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公开(公告)号：US09280479B1
公开(公告)日：2016-03-08
申请号：US13478100
申请日：2012-05-22
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F9/3824 , G06F12/0868 , G06F12/0897 , G06F2212/1024
摘要： A memory system having increased throughput is disclosed. Specifically, the memory system includes a first level write combining queue that reduces the number of data transfers between a level one cache and a level two cache. In addition, a second level write merging buffer can further reduce the number of data transfers within the memory system. The first level write combining queue receives data from the level one cache. The second level write merging buffer receives data from the first level write combining queue. The level two cache receives data from both the first level write combining queue and the second level write merging buffer. Specifically, the first level write combining queue combines multiple store transactions from the load store units to associated addresses. In addition, the second level write merging buffer merges data from the first level write combining queue.
摘要翻译： 公开了一种具有增加的吞吐量的存储器系统。 具体来说，存储器系统包括一级写入组合队列，其减少一级缓存和二级缓存之间的数据传输次数。 此外，第二级写入合并缓冲器可以进一步减少存储器系统内的数据传输的数量。 第一级写入组合队列从一级缓存接收数据。 第二级写合并缓冲区从第一级写入组合队列接收数据。 二级缓存从第一级写入组合队列和第二级写入合并缓冲区接收数据。 具体来说，第一级写入组合队列将来自加载存储单元的多个存储事务组合到相关联的地址。 另外，第二级写入合并缓冲区合并来自第一级写入组合队列的数据。
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公开(公告)号：US08850121B1
公开(公告)日：2014-09-30
申请号：US13250544
申请日：2011-09-30
IPC分类号： G06F12/08
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/34
摘要： A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. The outstanding load miss buffer stores a first missed load instruction in a first primary entry. Additional missed load instructions that are dependent on the first missed load instructions are stored in dependent entries of the first primary entry or in shared entries. If a shared entry is used for a missed load instruction the shared entry is associated with the primary entry.
摘要翻译： 具有未完成的负载未命中缓冲器和加载未命中结果缓冲器的加载/存储单元被配置为从具有一级缓存的存储器系统读取数据。 丢失的加载指令存储在未完成的负载丢失缓冲器中。 加载/存储单元使用单个高速缓存访问来检索多个相关的错过加载指令的数据，并将数据存储在加载未结果缓冲器中。 未完成的负载未命中缓冲存储器将第一个缺省加载指令存储在第一个初级条目中。 依赖于第一个错过的加载指令的附加的错过加载指令被存储在第一主入口的相关条目或共享条目中。 如果共享条目用于错过加载指令，则共享条目与主条目相关联。
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公开(公告)号：US08949581B1
公开(公告)日：2015-02-03
申请号：US13103833
申请日：2011-05-09
CPC分类号： G06F9/3834 , G06F9/3836 , G06F9/3842
摘要： A load scheduler capable of limited issuing of out of order load instruction is disclosed. The load scheduler uses a max skipping threshold which limits the number of skipping load instructions and a max skipped threshold which limits the number of skipped load instructions. An address tag for a skipping instruction is stored in a skipping load instruction tracking unit when a skipping load instruction is issued. When a skipped load instruction issues, the address tag of the skipped load instruction is compared to the address tag of the skipping instruction to determine if a hazard from the out of order issuing of the skipping load instruction caused a hazard and must be flushed.
摘要翻译： 公开了能够限制发出无序加载指令的负载调度器。 负载调度器使用限制跳过加载指令数量的最大跳过阈值和限制跳过加载指令数量的最大跳过阈值。 当发出跳过加载指令时，用于跳过指令的地址标签被存储在跳过加载指令跟踪单元中。 当跳过的加载指令发生时，将跳过的加载指令的地址标签与跳过指令的地址标签进行比较，以确定跳过加载指令的乱序发出的危险是否导致危险，并且必须被刷新。
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公开(公告)号：US08543843B1
公开(公告)日：2013-09-24
申请号：US11933349
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Carlos Puchol , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Carlos Puchol , Seungyoon Peter Song
CPC分类号： G06F9/3851
摘要： A virtual core management system including one or more physical cores, a virtual core including a collection of logical states associated with the execution of a program, and a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations.
摘要翻译： 包括一个或多个物理核心的虚拟核心管理系统，包括与执行程序相关联的逻辑状态集合的虚拟核心以及被配置为将所述虚拟核心映射到所述一个或多个物理内核之一的虚拟核心管理组件 基于电源管理的考虑。
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公开(公告)号：US08499293B1
公开(公告)日：2013-07-30
申请号：US11941912
申请日：2007-11-16
申请人： Matthew William Ashcraft , John Gregory Favor , Christopher Patrick Nelson , Ivan Pavle Radivojevic , Joseph Byron Rowlands , Richard Win Thaik
发明人： Matthew William Ashcraft , John Gregory Favor , Christopher Patrick Nelson , Ivan Pavle Radivojevic , Joseph Byron Rowlands , Richard Win Thaik
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include associating with each register a symbolic expression selected from a set of possible symbolic expressions, locating an operation, if any, that is next within the sequence of operations and setting that operation to be a working operation, where the working operation has associated therewith a destination register and zero or more source registers, and processing the working operation when the working operation and any symbolic expressions of its source registers, if any, match at least one of a set of rules, where each rule specifies that the working operation must match a subset of the operation set, where each rule also specifies that the symbolic expressions, if any, of any source registers of the working operation must match a subset of the possible symbolic expressions, and where the rule also specifies a result, then posting the result as the symbolic expression of the destination register.
摘要翻译： 公开了一种用于优化适于由处理器执行的操作序列的方法和装置，以包括将每个寄存器与从一组可能的符号表达式中选择的符号表达式相关联，定位下一个在 操作并将操作设置为工作操作，其中工作操作与目标寄存器和零个或多个源寄存器相关联，并且当工作操作和其源寄存器的任何符号表达（如果有的话）匹配时，处理工作操作 一组规则中的至少一个，其中每个规则规定工作操作必须与操作集的子集匹配，其中每个规则还规定工作操作的任何源寄存器的符号表达式（如果有的话）必须匹配 可能的符号表达式的子集，以及规则还指定结果的位置，然后将结果作为符号表达过程发布 目的地寄存器。
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公开(公告)号：US08037285B1
公开(公告)日：2011-10-11
申请号：US11880882
申请日：2007-07-23
申请人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar , Matthew William Ashcraft , Ivan Pavle Radivojevic
发明人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar , Matthew William Ashcraft , Ivan Pavle Radivojevic
IPC分类号： G06F15/00
CPC分类号： G06F12/0875 , G06F9/3017 , G06F9/30189 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： An instruction processing circuit includes a decoder circuit operable to receive a sequence of instructions and to decode the received sequence of instructions into a first type of sequence of operations, and a trace builder circuit operable to receive at least a portion of the sequence of operations of the first type and to generate, based thereon, a second type of sequence of operations, where the at least a portion of the sequence of operations of the first type represents a first portion of the sequence of instructions, where the first portion of the sequence of instructions includes at most one conditional control transfer instruction that, when present, ends the first portion of the sequence of instructions, and where the sequence of operations of the second type also represents the first portion of the sequence of instructions.
摘要翻译： 指令处理电路包括解码器电路，其可操作以接收指令序列并且将接收的指令序列解码为第一类型的操作序列，以及跟踪构建器电路，其可操作以接收至少一部分操作序列 第一类型并基于此产生第二类型的操作序列，其中第一类型的操作序列的至少一部分表示指令序列的第一部分，其中序列的第一部分 指令包括最多一个条件控制传输指令，当存在时，结束指令序列的第一部分，并且第二类型的操作序列也表示指令序列的第一部分。
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公开(公告)号：US08032710B1
公开(公告)日：2011-10-04
申请号：US11782163
申请日：2007-07-24
IPC分类号： G06F13/00
CPC分类号： G06F9/30072 , G06F9/3804 , G06F9/3808 , G06F9/3812 , G06F9/3836
摘要： A method and system of ensuring coherency of a sequence of instructions to be executed by a processor having a trace unit and an execution unit includes grouping at least a portion of the sequence of instructions to form at least one trace where a status of the at least one trace is set to a verified status when the at least one trace is formed; holding in the at least one trace a coherency component that includes a pointer to a physical address of the at least one trace; receiving, based on the coherency component, the pointer to the physical address as associated with an invalidating event, and in response thereto, setting the status of the at least one trace to be an unverified status; and preventing the at least one trace from being executed when the status of the at least one trace is the unverified status.
摘要翻译： 一种确保要由具有跟踪单元和执行单元的处理器执行的指令序列的一致性的方法和系统包括对指令序列的至少一部分进行分组，以形成至少一个跟踪，其中该至少一个状态至少 当形成至少一条迹线时，将一条迹线设置为已验证状态; 在所述至少一个跟踪中保持包括指向所述至少一个跟踪的物理地址的指针的相关性组件; 基于所述一致性分量接收与无效事件相关联的到所述物理地址的指针，并且响应于此，将所述至少一个跟踪的状态设置为未验证状态; 以及当所述至少一个跟踪的状态是未验证状态时，防止所述至少一个跟踪被执行。
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公开(公告)号：US08010745B1
公开(公告)日：2011-08-30
申请号：US12030859
申请日：2008-02-13
CPC分类号： G06F9/3808 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3861
摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. When a memory operation attempts to update a cache line that may not be updated, the circuit attempts to upgrade the cache line. If this fails, a rollback request is generated that indicates the trace involved. The checkpoint locations associated with the indicated trace are overwritten along with those locations associated with all younger traces.
摘要翻译： 本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 检查点条目与每个跟踪相关联。 当内存操作尝试更新可能未更新的高速缓存行时，该电路会尝试升级缓存行。 如果失败，则会生成一个回滚请求，指示涉及的跟踪。 与指示轨迹相关联的检查点位置与与所有较年轻轨迹相关联的那些位置被覆盖。
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