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34 条记录 (耗时 0.031 秒)

    Chip seal ring having a serpentine geometry
    4.
    发明授权
    Chip seal ring having a serpentine geometry 有权
    具有蛇形几何形状的芯片密封环

    公开(公告)号：US07466284B2

    公开(公告)日：2008-12-16

    申请号：US11564875

    申请日：2006-11-30

    申请人： Robert L. Barry

    发明人： Robert L. Barry

    IPC分类号： H01Q21/00

    CPC分类号： H01Q7/00 ,  H01L23/585 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01Q1/2283 ,  H01L2924/00

    摘要： A chip seal ring that maintains the chip seal ring as a continuous barrier to contamination, while at the same time creating a desirable electrical feature in the seal ring that enables the use of an on-chip loop antenna. In one embodiment, at least a portion of the chip seal ring has a serpentine configuration, such as a square wave, triangle wave, or curved geometry, that increases the reactance and resistance of the seal ring so as to mitigate the adverse induced currents created by the magnetic coupling effects between the on-chip antenna and the seal rings, thereby improving the efficiency of an on-chip loop antenna in the presence of the seal ring.

    摘要翻译： 芯片密封环，其将芯片密封环保持为污染的连续屏障，同时在密封环中产生期望的电特征，使得能够使用片上环形天线。 在一个实施例中，芯片密封环的至少一部分具有蛇形结构，例如方波，三角波或弯曲几何形状，其增加了密封环的电抗和电阻，以便减轻产生的不利的感应电流 通过片上天线和密封环之间的磁耦合效应，从而在存在密封环的情况下提高片上环形天线的效率。

    Serial input shift register built-in self test circuit for embedded circuits
    5.
    发明授权
    Serial input shift register built-in self test circuit for embedded circuits 失效
    串行输入移位寄存器内置嵌入式电路自检电路

    公开(公告)号：US5825785A

    公开(公告)日：1998-10-20

    申请号：US653572

    申请日：1996-05-24

    申请人： Robert L. Barry ,  John D. Chickanosky ,  Steven F. Oakland ,  Michael R. Ouellette

    发明人： Robert L. Barry ,  John D. Chickanosky ,  Steven F. Oakland ,  Michael R. Ouellette

    IPC分类号： G01R31/3181 ,  G01R31/3185 ,  G01R31/28

    CPC分类号： G01R31/3185 ,  G01R31/31813 ,  G06F2201/83

    摘要： A highly functional built in self test circuit for embedded compiled macros is useful for testing embedded compiled macros having differing parameters. The built in self test circuit receives a scan vector that describes the parameters of the embedded compiled macro that is to be tested. For, example, the number and width of words stored in a read only memory (ROM) are scanned into the built in self test circuit for controlling the test sequences. A state machine within the built in self test circuit cycles through test vector generation, test vector application, data output scanning and compression for signature analysis. Parallel outputs of the embedded compiled devices are serialized so that regardless of the number of outputs, a serial input shift register can be used for signature generation.

    摘要翻译： 用于嵌入式编译宏的高度内置的自测电路对于测试具有不同参数的嵌入式编译宏非常有用。 内建的自检电路接收一个描述被测试的嵌入式编译宏的参数的扫描向量。 例如，存储在只读存储器（ROM）中的字的数量和宽度被扫描到用于控制测试序列的内置自测试电路中。 内置自检电路中的状态机通过测试向量生成，测试向量应用，数据输出扫描和压缩进行签名分析。 嵌入式编译器件的并行输出被串行化，所以无论输出数量多少，都可以使用串行输入移位寄存器进行签名生成。

    Device and method for remote zeroing of a biological fluid pressure measurement device
    6.
    发明授权
    Device and method for remote zeroing of a biological fluid pressure measurement device 失效
    生物流体压力测量装置远程调零的装置和方法

    公开(公告)号：US5691478A

    公开(公告)日：1997-11-25

    申请号：US478300

    申请日：1995-06-07

    申请人： Robert L. Barry ,  Robert F. Alexander

    发明人： Robert L. Barry ,  Robert F. Alexander

    IPC分类号： A61B5/0215 ,  A61B5/0235 ,  G01L19/02 ,  G01L9/06

    CPC分类号： G01L19/02 ,  A61B5/02152 ,  A61B5/0235 ,  A61B2560/0261

    摘要： A device and method for remotely zeroing a hydrostatic pressure compensation device are described which permit a fluid transducer, such as is used in conjunction with an intravenous catheter for the measurement of blood pressure, to be zeroed regardless of its elevation. A hydrostatic pressure compensation tube is placed in closed fluid communication with both faces of the transducer so as to provide the same pressure to each side. As an example, the transducer may measure the deflection with a piezoresistive or piezoelectric crystal or may alternatively utilize a semiconductor membrane with implanted resistive elements. The transducer may be coupled or formed integral to a manifold. In such a device, the transducer may be zeroed at any vertical position.

    摘要翻译： 描述了用于远程调零流体静力压力补偿装置的装置和方法，其允许诸如与用于测量血压的静脉内导管结合使用的流体换能器被调零而不管其高度如何。 静压补偿管被放置在与换能器的两个表面封闭的流体连通中，以便向每一侧提供相同的压力。 作为示例，传感器可以使用压阻晶体或压电晶体来测量偏转，或者可选地使用具有注入的电阻元件的半导体膜。 换能器可以与歧管一体地联接或形成。 在这种装置中，换能器可以在任何垂直位置被归零。

    Complementary two transistor ROM cell
    8.
    发明授权
    Complementary two transistor ROM cell 有权
    互补的两个晶体管ROM单元

    公开(公告)号：US06778419B2

    公开(公告)日：2004-08-17

    申请号：US10063212

    申请日：2002-03-29

    申请人： Robert L. Barry ,  Peter F. Croce ,  Steven M. Eustis ,  Yabin Wang

    发明人： Robert L. Barry ,  Peter F. Croce ,  Steven M. Eustis ,  Yabin Wang

    IPC分类号： G11C1700

    CPC分类号： G11C17/12

    摘要： A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

    摘要翻译： 只读存储器（ROM）单元阵列的方法和结构具有连接到互补位线的第一晶体管的第一漏极和第二晶体管的第二漏极，第二晶体管连接到真位线和第二晶体管的第二漏极。 第一晶体管还包括第一源极，第二晶体管包括第二源极。 第一个源或第二个源到地面的连接将ROM单元编程。 利用本发明，只有第一源或第二源连接到地，而另一个与电连接绝缘。 此外，源极与地的连接包括在制造第一晶体管和第二晶体管期间形成的电连接。

    Ablation system with catheter clearing abrasive
    9.
    发明授权
    Ablation system with catheter clearing abrasive 有权
    消融系统与导管清除磨料

    公开(公告)号：US06632230B2

    公开(公告)日：2003-10-14

    申请号：US09835130

    申请日：2001-04-12

    申请人： Robert L. Barry

    发明人： Robert L. Barry

    IPC分类号： A61B1722

    CPC分类号： A61B17/320758 ,  A61B17/32075 ,  A61B2017/320004 ,  A61B2017/32008 ,  A61B2017/320775

    摘要： An ablation system comprising an atherectomy device and an aspiration catheter, each routed to a position just proximal to a lesion within a patient's vessel to ablate the lesion. The atherectomy device includes a flexible driveshaft coupled to an ablation burr. The ablation burr includes a concave front surface and a generally frusto-conical rear surface, both having an abrasive disposed thereon. The aspiration catheter has an elongate body and includes a centrally located lumen. The distal portion of the lumen is frusto-conical in shape and is positioned at the distal end of the catheter to define an aspiration mouth. The taper of the frusto-conical portion of the lumen corresponds to the taper of the rear surface of the ablation burr so that the ablation burr may be pulled back into the distal portion of the lumen of the catheter during operation of the system to clear captured ablated material therein.

    摘要翻译： 一种消融系统，其包括粥样斑块切除装置和抽吸导管，每个导管插入到病人血管内的病变附近的位置以消融病变。 粥样斑块切除装置包括耦合到消融毛刺的柔性驱动轴。 消融毛刺包括凹面前表面和大致截头圆锥形的后表面，两者都具有设置在其上的磨料。 抽吸导管具有细长体并且包括位于中心的内腔。 内腔的远端部分是截头圆锥形的并且位于导管的远端以限定抽吸口。 腔的截头圆锥形部分的锥度对应于消融毛刺的后表面的锥度，使得消除毛刺可以在系统的操作期间被拉回导管的内腔的远端部分以清除被捕获的 烧伤材料。

    Read only memory having localized reference bit lines
    10.
    发明授权
    Read only memory having localized reference bit lines 失效
    只读具有局部化参考位线的存储器

    公开(公告)号：US5602788A

    公开(公告)日：1997-02-11

    申请号：US660264

    申请日：1996-06-07

    申请人： Robert L. Barry ,  John D. Chickanosky

    发明人： Robert L. Barry ,  John D. Chickanosky

    IPC分类号： G11C17/12 ,  H01L27/112 ,  G11C7/00

    CPC分类号： H01L27/112 ,  G11C17/12

    摘要： A growable read only memory (ROM) provides improved performance over a wide range of array sizes by incorporating a localized reference bitline that accurately tracks changes in loading and variations in process parameters. The reference bitline is input into one side of a differential sense amplifier while a selected data bitline is input into the other side. The reference bitline is precharged and includes two columns, a first column includes devices that are matched to memory cell devices wherein a device of the selected word line will be selected to discharge the referenced bitline. The second column includes a recessed oxide device corresponding to each memory cell in the column. The combination of the two columns ensures that the reference bitline will discharge at a predetermined rate that tracks the rate at which a selected contact programmed memory cell discharges.

    摘要翻译： 可扩展的只读存储器（ROM）通过结合精确跟踪加载变化和过程参数变化的局部参考位线，在广泛的阵列大小范围内提供了改进的性能。 将参考位线输入到差分读出放大器的一侧，同时将选择的数据位线输入到另一侧。 参考位线被预充电并且包括两列，第一列包括与存储器单元器件匹配的器件，其中将选择所选择的字线的器件来放电所引用的位线。 第二列包括对应于列中的每个存储单元的凹陷氧化物装置。 两列的组合确保参考位线将以预定速率放电，该预定速率跟踪所选接触程序存储单元放电的速率。