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    CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION
    2.
    发明申请
    CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION 有权
    将消息信号中断转换为I / O适配器事件通知

    公开(公告)号：US20110321061A1

    公开(公告)日：2011-12-29

    申请号：US12821175

    申请日：2010-06-23

    申请人： David Craddock ,  Janet R. Easton ,  Mark S. Farrell ,  Thomas A. Gregg ,  Eric N. Lais ,  Gustav E. Sittmann, III

    发明人： David Craddock ,  Janet R. Easton ,  Mark S. Farrell ,  Thomas A. Gregg ,  Eric N. Lais ,  Gustav E. Sittmann, III

    IPC分类号： G06F9/44 ,  G06F13/24

    CPC分类号： G06F13/24 ,  G06F9/4812 ,  G06F2213/0026

    摘要： One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions.

    摘要翻译： 一个或多个来自一个或多个输入/输出（I / O）适配器的信号中断请求被转换为I / O适配器事件通知。 每个I / O适配器事件通知包括系统内存中的一个或多个特定指示符的设置和中断请求，其中第一个会导致挂起的I / O适配器中断请求。 当I / O适配器中断的请求处于待处理状态时，后续的消息信号中断请求将转换为I / O适配器事件通知，但不会导致对I / O适配器中断的其他请求。

    Associating input/output device requests with memory associated with a logical partition
    7.
    发明授权
    Associating input/output device requests with memory associated with a logical partition 有权
    将输入/输出设备请求与与逻辑分区关联的内存相关联

    公开(公告)号：US08417911B2

    公开(公告)日：2013-04-09

    申请号：US12821224

    申请日：2010-06-23

    申请人： David Craddock ,  Thomas A. Gregg ,  Eric N. Lais

    发明人： David Craddock ,  Thomas A. Gregg ,  Eric N. Lais

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00

    CPC分类号： G06F13/16 ,  G06F2213/0026

    摘要： An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory.

    摘要翻译： 地址控制器包括位选择器，其接收请求者id的第一部分，并从标识请求功能是SR-IOV设备还是标准PCIe设备的向量中选择一个位。 控制器还包括耦合到比特选择器的选择器，其基于从选择器接收的输入形成由RID的第二部分或地址部分的第一部分组成的输出，以及接收第一部分的地址控制单元 的RID和输出，并且基于此来确定拥有请求功能的LPAR，地址控制单元向存储器提供校正的存储器请求。

    TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES
    8.
    发明申请
    TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES 有权
    输入/输出地址到存储器地址的翻译

    公开(公告)号：US20110320758A1

    公开(公告)日：2011-12-29

    申请号：US12821170

    申请日：2010-06-23

    申请人： David Craddock ,  Thomas A. Gregg ,  Dan F. Greiner ,  Eric N. Lais

    发明人： David Craddock ,  Thomas A. Gregg ,  Dan F. Greiner ,  Eric N. Lais

    IPC分类号： G06F12/10

    CPC分类号： G06F12/10 ,  G06F9/355 ,  G06F12/0292 ,  G06F2212/206

    摘要： An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

    摘要翻译： 将由适配器发出的请求中提供的地址转换为直接用于访问系统内存的地址。 该地址包括多个比特，其中多个比特包括比特的第一部分和比特的第二部分。 比特的第二部分用于索引到一个或多个地址转换表中以执行转换，而第一部分比特被忽略用于转换。 位的第一部分用于验证地址。

    ASSOCIATING INPUT/OUTPUT DEVICE REQUESTS WITH MEMORY ASSOCIATED WITH A LOGICAL PARTITION
    10.
    发明申请
    ASSOCIATING INPUT/OUTPUT DEVICE REQUESTS WITH MEMORY ASSOCIATED WITH A LOGICAL PARTITION 有权
    与逻辑分区相关联的输入/输出设备请求

    公开(公告)号：US20110320703A1

    公开(公告)日：2011-12-29

    申请号：US12821224

    申请日：2010-06-23

    申请人： David Craddock ,  Thomas A. Gregg ,  Eric N. Lais

    发明人： David Craddock ,  Thomas A. Gregg ,  Eric N. Lais

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G06F13/16 ,  G06F2213/0026

    摘要： An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory.

    摘要翻译： 地址控制器包括位选择器，其接收请求者id的第一部分，并从标识请求功能是SR-IOV设备还是标准PCIe设备的向量中选择一位。 控制器还包括耦合到比特选择器的选择器，其基于从选择器接收的输入形成由RID的第二部分或地址部分的第一部分组成的输出，以及接收第一部分的地址控制单元 的RID和输出，并且基于此来确定拥有请求功能的LPAR，地址控制单元向存储器提供校正的存储器请求。