公开(公告)号：US20060273841A1

公开(公告)日：2006-12-07

申请号：US11160056

申请日：2005-06-07

申请人： David Hanson ,  Dureseti Chidambarrao ,  Gregory Fredeman ,  David Onsongo

发明人： David Hanson ,  Dureseti Chidambarrao ,  Gregory Fredeman ,  David Onsongo

IPC分类号： H01H37/76

CPC分类号： G11C17/18

摘要： A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor (“multi-state FET”) having at least one of a source or a drain coupled to the electrically alterable element to apply a current to the electrically alterable element. The multi-state FET has a first threshold voltage and a second threshold voltage, both being effective at the same time, the second threshold voltage being higher than the first threshold voltage. The gate is operable to control operation of the multi-state FET in multiple states including a) an essentially nonconductive state; b) a first or “low” conductive state when a gate-source voltage exceeds the first threshold voltage, in which the multi-state FET is biased to conduct a relatively low magnitude current for determining the state of the fuse; and c) a second conductive state when the gate-source voltage exceeds the second threshold voltage, in which the multi-state FET is biased to conduct a relatively high magnitude programming current.

摘要翻译： 提供了一种电路，其可操作以将电可更改元件（例如，熔丝或反熔丝）编程到编程状态，并确定电可更改元件是否处于编程状态。 这种电路包括多导通状态场效应晶体管（“多状态FET”），其具有耦合到可电可变元件的源极或漏极中的至少一个，以将电流施加到电可更改元件。 多状态FET具有第一阈值电压和第二阈值电压，两者均同时有效，第二阈值电压高于第一阈值电压。 栅极可操作以控制多状态FET的操作，包括a）基本上非导通状态; b）当栅极 - 源极电压超过第一阈值电压时，第一或“低”导通状态，其中多态FET被偏置以传导相对低的幅度电流以确定保险丝的状态; 以及c）当所述栅极 - 源极电压超过所述第二阈值电压时，所述第二导电状态是所述多态FET被偏置以导通相对高的编程电流。

公开(公告)号：US20060273393A1

公开(公告)日：2006-12-07

申请号：US11160055

申请日：2005-06-07

申请人： Dureseti Chidambarrao ,  David Onsongo ,  David Hanson

发明人： Dureseti Chidambarrao ,  David Onsongo ,  David Hanson

IPC分类号： H01L29/43

CPC分类号： H01L21/2822 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/518

摘要： A field effect transistor (“FET”) is provided has a semiconductor region including a channel region, a source region and a drain region and a gate conductor overlying the channel region. Such FET has a first threshold voltage having a first magnitude and a second threshold voltage having a second magnitude higher than the first magnitude, both threshold voltages being effective at the same time. The FET is operable in response to a gate-source voltage between the gate conductor and the source region in multiple states including at least: a) an essentially nonconductive state when a magnitude of the gate-source voltage is less than the first magnitude and less than the second magnitude, the source-drain current then being at most a negligible value; b) a first conductive state when the magnitude of the gate-source voltage is greater than the first magnitude and less than the second magnitude, the source-drain current then having a first operating value about ten or more times higher than the negligible value; and c) a second conductive state when the magnitude of the gate-source voltage is greater than first magnitude and the second magnitude, in which state the source-drain current has a second operating value ten or more times higher than the first operating value.

摘要翻译： 提供场效应晶体管（“FET”）具有包括沟道区，源极区和漏极区以及覆盖沟道区的栅极导体的半导体区。 这样的FET具有第一阈值电压和第二阈值电压，第一阈值电压具有比第一幅度高的第二幅度，两个阈值电压同时有效。 FET可响应于多个状态的栅极导体和源极区域之间的栅极 - 源极电压而工作，包括至少：a）当栅极 - 源极电压的幅度小于第一个幅度并且较小时，基本上是非导通状态 那么源极 - 漏极电流最大可以忽略不计。 b）当栅极 - 源极电压的大小大于第一幅度且小于第二幅度时，第一导电状态，源极 - 漏极电流的第一个操作值比可忽略的值高大约十倍或更多倍; 以及c）当所述栅极 - 源极电压的大小大于所述第一幅度和所述第二幅度时，所述第二导通状态，其中所述源极 - 漏极电流具有比所述第一操作值高十倍或更多倍的第二操作值。

公开(公告)号：US20070257249A1

公开(公告)日：2007-11-08

申请号：US11381810

申请日：2006-05-05

申请人： Anda Mocuta ,  Dureseti Chidambarrao ,  Ricardo Donaton ,  David Onsongo ,  Kern Rim

发明人： Anda Mocuta ,  Dureseti Chidambarrao ,  Ricardo Donaton ,  David Onsongo ,  Kern Rim

IPC分类号： H01L31/00

CPC分类号： H01L21/823807 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78687

摘要： A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.

摘要翻译： 一种制造半导体器件的半导体结构和方法，特别是NFET器件。 这些装置包括在应力诱导层上提供的应力接收层，其中在其间的界面处的材料减少了结构中失配位错的发生和传播。 应力接收层是硅（Si），应力诱导层是硅锗（SiGe），并且材料是在形成器件期间通过掺杂层提供的碳。 也可以在整个SiGe层中掺杂碳。

公开(公告)号：US20070028195A1

公开(公告)日：2007-02-01

申请号：US11193711

申请日：2005-07-29

申请人： Dureseti Chidambarrao ,  Donald Jordan ,  Judith McCullen ,  David Onsongo ,  Tina Wagner ,  Richard Williams

发明人： Dureseti Chidambarrao ,  Donald Jordan ,  Judith McCullen ,  David Onsongo ,  Tina Wagner ,  Richard Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

摘要： System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).

摘要翻译： 用于紧凑模型算法的系统和方法来准确地解释半导体器件中氮化物衬垫应力的布局引起的变化的影响。 布局敏感的压缩模型算法通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。 特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。 算法还适用于使具有单个应力衬垫膜和双应力衬垫（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击确定。

公开(公告)号：US20070252212A1

公开(公告)日：2007-11-01

申请号：US11380278

申请日：2006-04-26

申请人： David Onsongo ,  Werner Rausch ,  Haining Yang

发明人： David Onsongo ,  Werner Rausch ,  Haining Yang

IPC分类号： H01L23/62

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

摘要翻译： 本发明提供了具有双栅极导体的改进的CMOS二极管结构。 具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。 此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。 可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度 导体。