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    STRUCTURE AND METHOD OF MAKING FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES
    1.
    发明申请
    STRUCTURE AND METHOD OF MAKING FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES 失效
    制造具有多个导电状态的场效应晶体管的结构和方法

    公开(公告)号：US20060273393A1

    公开(公告)日：2006-12-07

    申请号：US11160055

    申请日：2005-06-07

    申请人： Dureseti Chidambarrao ,  David Onsongo ,  David Hanson

    发明人： Dureseti Chidambarrao ,  David Onsongo ,  David Hanson

    IPC分类号： H01L29/43

    CPC分类号： H01L21/2822 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/518

    摘要： A field effect transistor (“FET”) is provided has a semiconductor region including a channel region, a source region and a drain region and a gate conductor overlying the channel region. Such FET has a first threshold voltage having a first magnitude and a second threshold voltage having a second magnitude higher than the first magnitude, both threshold voltages being effective at the same time. The FET is operable in response to a gate-source voltage between the gate conductor and the source region in multiple states including at least: a) an essentially nonconductive state when a magnitude of the gate-source voltage is less than the first magnitude and less than the second magnitude, the source-drain current then being at most a negligible value; b) a first conductive state when the magnitude of the gate-source voltage is greater than the first magnitude and less than the second magnitude, the source-drain current then having a first operating value about ten or more times higher than the negligible value; and c) a second conductive state when the magnitude of the gate-source voltage is greater than first magnitude and the second magnitude, in which state the source-drain current has a second operating value ten or more times higher than the first operating value.

    摘要翻译： 提供场效应晶体管（“FET”）具有包括沟道区，源极区和漏极区以及覆盖沟道区的栅极导体的半导体区。 这样的FET具有第一阈值电压和第二阈值电压，第一阈值电压具有比第一幅度高的第二幅度，两个阈值电压同时有效。 FET可响应于多个状态的栅极导体和源极区域之间的栅极 - 源极电压而工作，包括至少：a）当栅极 - 源极电压的幅度小于第一个幅度并且较小时，基本上是非导通状态 那么源极 - 漏极电流最大可以忽略不计。 b）当栅极 - 源极电压的大小大于第一幅度且小于第二幅度时，第一导电状态，源极 - 漏极电流的第一个操作值比可忽略的值高大约十倍或更多倍; 以及c）当所述栅极 - 源极电压的大小大于所述第一幅度和所述第二幅度时，所述第二导通状态，其中所述源极 - 漏极电流具有比所述第一操作值高十倍或更多倍的第二操作值。

    PROGRAMMING AND DETERMINING STATE OF ELECTRICAL FUSE USING FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES
    2.
    发明申请
    PROGRAMMING AND DETERMINING STATE OF ELECTRICAL FUSE USING FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES 失效
    使用具有多个导通状态的场效应晶体管编程和确定电子熔丝状态

    公开(公告)号：US20060273841A1

    公开(公告)日：2006-12-07

    申请号：US11160056

    申请日：2005-06-07

    申请人： David Hanson ,  Dureseti Chidambarrao ,  Gregory Fredeman ,  David Onsongo

    发明人： David Hanson ,  Dureseti Chidambarrao ,  Gregory Fredeman ,  David Onsongo

    IPC分类号： H01H37/76

    CPC分类号： G11C17/18

    摘要： A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor (“multi-state FET”) having at least one of a source or a drain coupled to the electrically alterable element to apply a current to the electrically alterable element. The multi-state FET has a first threshold voltage and a second threshold voltage, both being effective at the same time, the second threshold voltage being higher than the first threshold voltage. The gate is operable to control operation of the multi-state FET in multiple states including a) an essentially nonconductive state; b) a first or “low” conductive state when a gate-source voltage exceeds the first threshold voltage, in which the multi-state FET is biased to conduct a relatively low magnitude current for determining the state of the fuse; and c) a second conductive state when the gate-source voltage exceeds the second threshold voltage, in which the multi-state FET is biased to conduct a relatively high magnitude programming current.

    摘要翻译： 提供了一种电路，其可操作以将电可更改元件（例如，熔丝或反熔丝）编程到编程状态，并确定电可更改元件是否处于编程状态。 这种电路包括多导通状态场效应晶体管（“多状态FET”），其具有耦合到可电可变元件的源极或漏极中的至少一个，以将电流施加到电可更改元件。 多状态FET具有第一阈值电压和第二阈值电压，两者均同时有效，第二阈值电压高于第一阈值电压。 栅极可操作以控制多状态FET的操作，包括a）基本上非导通状态; b）当栅极 - 源极电压超过第一阈值电压时，第一或“低”导通状态，其中多态FET被偏置以传导相对低的幅度电流以确定保险丝的状态; 以及c）当所述栅极 - 源极电压超过所述第二阈值电压时，所述第二导电状态是所述多态FET被偏置以导通相对高的编程电流。

    System and method for controlling intelligent animated characters
    4.
    发明授权
    System and method for controlling intelligent animated characters 有权

    公开(公告)号：US09796095B1

    公开(公告)日：2017-10-24

    申请号：US13968241

    申请日：2013-08-15

    申请人： David Hanson ,  Robert Hauser

    发明人： David Hanson ,  Robert Hauser

    IPC分类号： G06F19/00 ,  G05B19/04 ,  B25J11/00

    CPC分类号： B25J11/0005 ,  B25J11/001

    摘要： A system and method for controlling animated characters. The system involves an animated character mapping perception into a number of domains, including a world domain, linguistic domain and social domain. The system is computationally perceived items that should be abstracted from the character's environment for processing. The animated character is able to utilize different levels of information gathering or learning, different levels of decision making, and different levels of dynamic responses to provide life-like interactions.

    Email SMS notification system providing enhanced message retrieval features and related methods
    6.
    发明申请
    Email SMS notification system providing enhanced message retrieval features and related methods 有权
    电子邮件短信通知系统，提供增强的消息检索功能和相关方法

    公开(公告)号：US20060293032A1

    公开(公告)日：2006-12-28

    申请号：US11165309

    申请日：2005-06-23

    申请人： David Clarke ,  Harshad Kamat ,  David Hanson

    发明人： David Clarke ,  Harshad Kamat ,  David Hanson

    IPC分类号： H04Q7/22

    CPC分类号： H04L51/24 ,  H04L51/38 ,  H04W4/12 ,  H04W4/14 ,  H04W88/06 ,  H04W88/184 ,  H04W92/02

    摘要： A communications system may include at least one wireless communications device and at least one electronic mail (email) server for storing email messages for the at least one wireless communications device. The system may further include an email relay server for detecting a new email message on the at least one email server and, based thereon, sending a short message service (SMS) notification with a unique message identifier (ID) of the new email message to the at least one wireless communications device. Moreover, the at least one wireless communications device may detect the SMS notification and send an email retrieval request to the email relay server instructing the email relay server to retrieve the new email message based upon the unique message ID.

    摘要翻译： 通信系统可以包括至少一个无线通信设备和用于存储用于至少一个无线通信设备的电子邮件消息的至少一个电子邮件（电子邮件）服务器。 系统还可以包括用于在至少一个电子邮件服务器上检测新的电子邮件消息的电子邮件中继服务器，并且基于此，发送具有新电子邮件消息的唯一消息标识符（ID）的短消息服务（SMS）通知， 所述至少一个无线通信设备。 此外，所述至少一个无线通信设备可以检测SMS通知，并且向电子邮件中继服务器发送电子邮件检索请求，其指示电子邮件中继服务器基于唯一的消息ID来检索新的电子邮件消息。

    LOW POWER MANAGER FOR STANDBY OPERATION OF A MEMORY SYSTEM
    7.
    发明申请
    LOW POWER MANAGER FOR STANDBY OPERATION OF A MEMORY SYSTEM 有权
    低功耗管理器，用于存储系统的待机操作

    公开(公告)号：US20060039226A1

    公开(公告)日：2006-02-23

    申请号：US11205565

    申请日：2005-08-17

    申请人： David Hanson ,  Gregory Fredeman ,  John Golz ,  Hoki Kim ,  Paul Parries

    发明人： David Hanson ,  Gregory Fredeman ,  John Golz ,  Hoki Kim ,  Paul Parries

    IPC分类号： G11C5/14

    CPC分类号： G11C5/143 ,  G11C8/08

    摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

    摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

    MICROELECTRONIC ELEMENT HAVING TRENCH CAPACITORS WITH DIFFERENT CAPACITANCE VALUES
    8.
    发明申请
    MICROELECTRONIC ELEMENT HAVING TRENCH CAPACITORS WITH DIFFERENT CAPACITANCE VALUES 失效
    具有不同电容值的电容器的微电子元件

    公开(公告)号：US20050280063A1

    公开(公告)日：2005-12-22

    申请号：US10710146

    申请日：2004-06-22

    申请人： Kangguo Cheng ,  Johnathan Faltermeier ,  David Hanson ,  Carl Radens

    发明人： Kangguo Cheng ,  Johnathan Faltermeier ,  David Hanson ,  Carl Radens

    IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/66181 ,  H01L27/1087 ,  H01L27/10894 ,  H01L29/945

    摘要： A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface.

    摘要翻译： 提供具有主表面的微电子元件，微电子元件包括形成在第一沟槽的侧壁上的第一电容器，第一沟槽从主表面沿向下延伸的方向伸长。 微电子元件还包括形成在第二沟槽的侧壁上的第二电容器，第二沟槽从主表面沿向下延伸的方向伸长，其中第一电容器的顶部设置在距离主表面的第一深度处， 并且第二电容器的顶部设置在距离主表面的第二深度处。

    UNIVERSAL CMOS DEVICE LEAKAGE CHARACTERIZATION SYSTEM
    10.
    发明申请
    UNIVERSAL CMOS DEVICE LEAKAGE CHARACTERIZATION SYSTEM 有权
    通用CMOS器件泄漏特性系统

    公开(公告)号：US20070252613A1

    公开(公告)日：2007-11-01

    申请号：US11380515

    申请日：2006-04-27

    申请人： Louis Hsu ,  Edward Pillai ,  Joseph Natonio ,  James Rockrohr ,  David Hanson

    发明人： Louis Hsu ,  Edward Pillai ,  Joseph Natonio ,  James Rockrohr ,  David Hanson

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2884 ,  G01R31/3008 ,  G01R31/318577

    摘要： The invention provides a universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-threshold leakage, and the reverse biased junction leakage, and the like. Testing is performed sequentially from the first test macro up to the last test macro using an on-chip algorithm. When the last test macro is tested, it scans the leakage data out.

    摘要翻译： 本发明提供了一种通用泄漏监测系统（ULMS），用于在开发制造过程或正常操作期期间测量多个泄漏宏。 ULMS表征了栅极电介质泄漏，亚阈值泄漏和反向偏置结漏电以及n型和p型CMOS器件的泄漏等。 使用片上算法从第一测试宏到最后一个测试宏顺序执行测试。 当测试最后一个测试宏时，会扫描泄漏数据。