公开(公告)号：US07657694B2

公开(公告)日：2010-02-02

申请号：US11641969

申请日：2006-12-20

申请人： David Hennah Mansell ,  Stuart David Biles ,  Stephen John Hill

发明人： David Hennah Mansell ,  Stuart David Biles ,  Stephen John Hill

IPC分类号： G06F21/00

CPC分类号： G06F13/24

摘要： A data processing apparatus is provided comprising processing logic for issuing access requests when access to data is required, with each access request specifying a memory address associated with the data the subject of the access request. Access control logic is used to perform an access control operation to check for each access request whether the specified memory address is accessible by the processing logic. Further, a table is provided having a plurality of entries, each entry identifying an address range and an associated action. On occurrence of one or more predetermined events, the access control logic references the table to determine whether the specified address is within the address range identified by an entry of the table. If so, the associated action specified in that entry is invoked, whereas otherwise the access control logic causes any action indicated by the access control operation to be performed. This provides a particularly efficient mechanism for handling access requests in a variety of situations, for example within a virtualization environment where the access requests are directed to virtual devices implemented by hypervisor software.

摘要翻译： 提供了一种数据处理装置，包括当需要访问数据时发出访问请求的处理逻辑，每个访问请求指定与访问请求的对象的数据相关联的存储器地址。 访问控制逻辑用于执行访问控制操作以检查每个访问请求是否由处理逻辑访问指定的存储器地址。 此外，提供具有多个条目的表，每个条目标识地址范围和相关联的动作。 在发生一个或多个预定事件时，访问控制逻辑引用该表以确定指定的地址是否在由表的条目标识的地址范围内。 如果是，则调用在该条目中指定的相关联的动作，而否则访问控制逻辑将导致执行由访问控制操作指示的任何动作。 这提供了用于在各种情况下处理访问请求的特别有效的机制，例如在其中访问请求被引导到由管理程序软件实现的虚拟设备的虚拟化环境中。

公开(公告)号：US20080155167A1

公开(公告)日：2008-06-26

申请号：US11641969

申请日：2006-12-20

申请人： David Hennah Mansell ,  Stuart David Biles ,  Stephen John Hill

发明人： David Hennah Mansell ,  Stuart David Biles ,  Stephen John Hill

IPC分类号： G06F12/08

CPC分类号： G06F13/24

摘要： A data processing apparatus is provided comprising processing logic for issuing access requests when access to data is required, with each access request specifying a memory address associated with the data the subject of the access request. Access control logic is used to perform an access control operation to check for each access request whether the specified memory address is accessible by the processing logic. Further, a table is provided having a plurality of entries, each entry identifying an address range and an associated action. On occurrence of one or more predetermined events, the access control logic references the table to determine whether the specified address is within the address range identified by an entry of the table. If so, the associated action specified in that entry is invoked, whereas otherwise the access control logic causes any action indicated by the access control operation to be performed. This provides a particularly efficient mechanism for handling access requests in a variety of situations, for example within a virtualisation environment where the access requests are directed to virtual devices implemented by hypervisor software.

摘要翻译： 提供了一种数据处理装置，包括当需要访问数据时发出访问请求的处理逻辑，每个访问请求指定与访问请求的对象的数据相关联的存储器地址。 访问控制逻辑用于执行访问控制操作以检查每个访问请求是否由处理逻辑访问指定的存储器地址。 此外，提供具有多个条目的表，每个条目标识地址范围和相关联的动作。 在发生一个或多个预定事件时，访问控制逻辑引用该表以确定指定的地址是否在由表的条目标识的地址范围内。 如果是，则调用在该条目中指定的相关联的动作，而否则访问控制逻辑将导致执行由访问控制操作指示的任何操作。 这提供了用于在各种情况下处理访问请求的特别有效的机制，例如在其中访问请求被定向到由管理程序软件实现的虚拟设备的虚拟化环境中。

公开(公告)号：US20100235579A1

公开(公告)日：2010-09-16

申请号：US12223173

申请日：2006-09-18

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/127 ,  G06F12/0862

摘要： A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.

摘要翻译： 提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。 数据处理装置具有用于执行指令序列的至少一个处理单元，每个这样的处理单元具有与其相关联的高速缓冲存储器，每个高速缓冲存储器具有多个高速缓存行，用于存储由相关联的处理单元执行访问时的数据值 指令序列 提供了识别逻辑，对于每个高速缓存来说，监视数据处理装置内的数据业务，并且基于此，生成用于驱逐的标识的优选，以便识别为驱逐优选的一个或多个数据值。 然后，对于每个高速缓存，缓存维护逻辑被设置为实现高速缓存维护操作，在该高速缓存维护操作期间，考虑到存储的数据值的识别逻辑生成的用于逐出识别​​的任何优选的执行，从该高速缓存中选择一个或多个数据值 在那个缓存中。 已经发现，这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。

公开(公告)号：US20090222816A1

公开(公告)日：2009-09-03

申请号：US12379082

申请日：2009-02-12

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F9/455

CPC分类号： G06F12/145

摘要： A data processing apparatus and method are provided for controlling access to secure memory by virtual machines executing on processing circuitry. The processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system is provided for storing data for access by the processing circuitry, the memory system comprising secure memory for storing secure data and non-secure memory for storing non-secure data, the secure memory only being accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address. A trusted virtual machine identifier is maintained and managed by the hypervisor software, with the hypervisor software setting the trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory. Accordingly, in response to the access request issued by the current virtual machine, the address translation circuitry is only able to cause the modified access request to be issued as a secure access request specifying a physical address within the secure memory if the trusted virtual machine identifier is set. By such an approach, the hypervisor software is able to support multiple virtual machines at least some of which have access to secure memory under conditions controlled by the hypervisor software.

摘要翻译： 提供了一种数据处理装置和方法，用于通过在处理电路上执行的虚拟机来控制对安全存储器的访问。 处理电路执行管理程序软件以支持处理电路上的多个虚拟机的执行。 提供了一种用于存储由处理电路进行访问的数据的存储器系统，该存储器系统包括用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器，该安全存储器仅可通过安全访问请求访问。 地址转换电路响应于指定虚拟地址的当前虚拟机发出的访问请求，执行地址转换处理以识别存储器中的物理地址，并且将经修改的访问请求发布到存储器系统指定 物理地址。 由管理程序软件维护和管理可信赖的虚拟机标识符，如果当前虚拟机被信任以访问安全存储器，则管理程序软件设置可信虚拟机标识符。 因此，响应于当前虚拟机发出的访问请求，地址转换电路仅能够将修改的访问请求作为指定安全存储器内的物理地址的安全访问请求发出，如果可信虚拟机标识符 被设置。 通过这种方法，管理程序软件能够支持多个虚拟机，其中至少一些虚拟机在由管理程序软件控制的条件下可以访问安全存储器。

公开(公告)号：US20070143515A1

公开(公告)日：2007-06-21

申请号：US11603091

申请日：2006-11-22

申请人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

发明人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

IPC分类号： G06F13/26

CPC分类号： G06F21/52 ,  G06F13/26

摘要： An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.

摘要翻译： 中断控制器2设置有优先级寄存器6，优先级寄存器6存储优先级值P 0 -P 9，用于确定接收到的中断信号I 0至I 9之间的优先级。 优先级值访问电路10根据优先权值管理器16,18存储的优先权值提供多个映射，寻求进行访问。 以这种方式，诸如安全操作系统的第一优先级值管理器18可以被授予对最高优先级值的排他访问，而可以给予诸如非安全操作系统的第二优先级值管理器16访问 所存储的优先级较低的范围的优先权较低，但由非安全操作系统写入或读取，对于非安全操作系统来说，具有不同的，例如较高的优先级。

公开(公告)号：US08418175B2

公开(公告)日：2013-04-09

申请号：US12379082

申请日：2009-02-12

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F9/00

CPC分类号： G06F12/145

摘要： Processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system stores data for access by the processing circuitry and includes secure memory and non-secure memory . The secure memory is only accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address. The hypervisor software sets a trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory. The address translation circuitry can only cause the modified access request to be issued as a secure access request to the secure memory if the trusted identifier is set.

摘要翻译： 处理电路执行管理程序软件以支持在处理电路上执行多个虚拟机。 存储器系统存储用于由处理电路访问的数据，并且包括安全存储器和非安全存储器。 安全存储器只能通过安全访问请求访问。 地址转换电路响应于指定虚拟地址的当前虚拟机发出的访问请求，执行地址转换处理以识别存储器中的物理地址，并且将经修改的访问请求发布到存储器系统指定 物理地址。 如果当前虚拟机被信任以访问安全存储器，则管理程序软件设置可信赖的虚拟机标识符。 如果设置了可信标识符，则地址转换电路只能使经修改的访问请求作为对安全存储器的安全访问请求发出。

公开(公告)号：US08041897B2

公开(公告)日：2011-10-18

申请号：US12223173

申请日：2006-09-18

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/127 ,  G06F12/0862

摘要： A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.

摘要翻译： 提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。 数据处理装置具有用于执行指令序列的至少一个处理单元，每个这样的处理单元具有与其相关联的高速缓存，每个高速缓冲存储器具有多个高速缓存行，用于存储由相关处理单元执行访问时的数据值 指令序列 提供了识别逻辑，对于每个高速缓存来说，监视数据处理装置内的数据业务，并且基于此，生成用于驱逐的标识的优选，以便识别为驱逐优选的一个或多个数据值。 然后，对于每个高速缓存，缓存维护逻辑被布置以实现高速缓存维护操作，在该高速缓存维护操作期间，考虑到存储的数据值的识别逻辑生成的用于逐出识别​​的任何优选的执行，从该缓存中选择一个或多个用于逐出的数据值 在那个缓存中。 已经发现，这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。

公开(公告)号：US07506091B2

公开(公告)日：2009-03-17

申请号：US11603091

申请日：2006-11-22

申请人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

发明人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

IPC分类号： G06F13/26 ,  G06F13/24 ,  G06F13/32

CPC分类号： G06F21/52 ,  G06F13/26

摘要： An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.

摘要翻译： 中断控制器2设置有优先级寄存器6，优先级寄存器6存储用于确定接收的中断信号I0-I9之间的优先级的优先权值P0-P9。 优先级值访问电路10根据优先权值管理器16,18存储的优先权值提供多个映射，寻求进行访问。 以这种方式，诸如安全操作系统的第一优先级值管理器18可以被授予对最高优先级值的排他访问，而可以给予诸如非安全操作系统的第二优先级值管理器16访问 所存储的优先级较低的范围的优先权较低，但由非安全操作系统写入或读取，对于非安全操作系统来说，具有不同的，例如较高的优先级。

公开(公告)号：US08041930B2

公开(公告)日：2011-10-18

申请号：US11919757

申请日：2005-05-11

申请人： David Hennah Mansell ,  Stuart David Biles ,  David Michael Gilday ,  Daniel Kershaw

发明人： David Hennah Mansell ,  Stuart David Biles ,  David Michael Gilday ,  Daniel Kershaw

IPC分类号： G06F9/00

CPC分类号： G06F9/30123 ,  G06F9/3012 ,  G06F9/3851

摘要： The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group.

摘要翻译： 数据处理装置具有用于执行数据处理操作的处理逻辑和用于存储与处理逻辑相关联的数据的寄存器组。 寄存器组具有至少一个寄存器组，每个寄存器组具有多个寄存器组。 处理逻辑具有与定义如何使用该寄存器组的每个寄存器组相关联的操作状态，第一操作状态是其中在寄存器组中设置的每个寄存器用于支持处理逻辑的独立执行线程的状态，以及 第二操作状态是将寄存器组的寄存器组集中用于支持处理逻辑的单个执行线程的状态。 提供控制逻辑以根据与该寄存器组相关联的操作状态来控制如何使用每个寄存器组的寄存器组。

公开(公告)号：US20090313455A1

公开(公告)日：2009-12-17

申请号：US11919210

申请日：2005-12-15

申请人： David Hennah Mansell ,  Stuart David Biles

发明人： David Hennah Mansell ,  Stuart David Biles

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857

摘要： A multithreaded processor is provided with a saturating counter which serves to generate a thread preference signal to steer selection of which program thread operations are taken from for issue into the multiple processor pipelines. The counter is updated based upon the selections made for issue. The counter is a saturating counter and its sign bit may be used as a thread preference signal when discriminating between two threads. The update made to the count value can be weighted depending upon programmable priorities associated with the respective threads as well as a weighting based upon the time taken to execute the type of operation selected.

摘要翻译： 多线程处理器设置有饱和计数器，其用于产生线程偏好信号以引导选择哪些程序线程操作被从多个处理器管线中发出。 计数器根据对问题的选择进行更新。 计数器是饱和计数器，并且当识别两个线程时，其符号位可以用作线程偏好信号。 对计数值进行的更新可以根据与相应线程相关联的可编程优先级加权，以及基于执行所选择的操作类型所花费的时间的加权。