公开(公告)号：US20050188182A1

公开(公告)日：2005-08-25

申请号：US11114549

申请日：2005-04-26

申请人： David Hoyle ,  Vishal Markandey ,  Lewis Nardini

发明人： David Hoyle ,  Vishal Markandey ,  Lewis Nardini

IPC分类号： G06F15/00

CPC分类号： G06F9/30032 ,  G06F9/30036 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3891

摘要： A data processing system is provided with a digital signal processor that has a set of instructions for intermingling byte fields selected from a selected pair of source operands and storing the ordered result in a selected destination register. A first 32-bit operand is treated as four 8-bit fields while a second 32-bit operand is treated as four 8-bit fields. Intermingling circuitry is operable to form an ordered result in accordance with each one of the set of byte intermingling instructions. An instruction is provided that performs a shift right and byte merge operation. Another instruction is provided that performs a shift left and byte merge operation. Another instruction is provided that perform a byte swap operation. A set of instructions are provided that perform various byte packing and unpacking operations.

摘要翻译： 数据处理系统具有数字信号处理器，该数字信号处理器具有一组指令，用于混合从所选择的一对源操作数中选择的字节字段，并将所选择的结果存储在所选择的目标寄存器中。 第一个32位操作数被视为四个8位字段，而第二个32位操作数被视为四个8位字段。 混合电路可操作以根据该组字节混合指令中的每一个形成有序结果。 提供执行右移和字节合并操作的指令。 另外提供了执行左移和字节合并操作的指令。 提供另一个执行字节交换操作的指令。 提供了一组执行各种字节打包和解包操作的指令。

公开(公告)号：US06745319B1

公开(公告)日：2004-06-01

申请号：US09702452

申请日：2000-10-31

申请人： Keith Balmer ,  David Hoyle ,  Lewis Nardini

发明人： Keith Balmer ,  David Hoyle ,  Lewis Nardini

IPC分类号： G06F9305

CPC分类号： G06F9/3891 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3885

摘要： A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the shuffled result in a selected destination register (610). A shuffled result is formed by interleaving bits from a first source operand portion with bits from a second operand portion. A de-interleave and pack (DEAL) instruction is provided for de-interleaving a source operand. The shuffle instruction and the DEAL instruction have an exactly inverse effect. The DSP includes swizzle circuitry that performs interleaving or de-interleaving in a single execution phase.

摘要翻译： 数据处理系统具有数字信号处理器（DSP），数字信号处理器（DSP）具有用于混洗源操作数（600）并将洗牌结果存储在所选目的地寄存器（610）中的混洗指令。 通过从来自第二操作数部分的位与第一源操作数部分交织比特来形成混洗结果。 提供去交错和包（DEAL）指令用于解交织源操作数。 随机播放指令和DEAL指令具有完全相反的效果。 DSP包括在单个执行阶段执行交织或解交织的交换电路。

公开(公告)号：US08655637B2

公开(公告)日：2014-02-18

申请号：US11566772

申请日：2006-12-05

申请人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

发明人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

IPC分类号： G06F9/455

CPC分类号： G06F11/3648 ,  G01R31/31703 ,  G01R31/31705 ,  G06F11/3656

摘要： An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.

摘要翻译： 存储器访问地址比较器包括将输入存储器访问地址与相应的参考地址进行比较的两个比较器。 比较器根据可选择的标准产生匹配指示，例如地址大小，全部或部分重叠，大于，小于，等于，不等于，小于等于并且大于或等于，并且可以是选择性地 链接。 输入多路复用器允许存储器访问地址总线选择。 比较器输出可以选择性地依赖于相应的数据匹配。 参考地址，比较数据和控制功能通过中央处理单元可访问存储器映射寄存器使能。

公开(公告)号：US07925687B2

公开(公告)日：2011-04-12

申请号：US11383335

申请日：2006-05-15

申请人： Manisha Agarwala ,  John M. Johnsen ,  Lewis Nardini

发明人： Manisha Agarwala ,  John M. Johnsen ,  Lewis Nardini

IPC分类号： G06F7/38

CPC分类号： G06F11/261

摘要： A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.

摘要翻译： 饱和计数将接收的事件信号计数到第一预定数量。 溢出计数器计数溢出到第二预定数量。 当溢出计数达到第二个预定数量时，计数器指示溢出计数不为零并饱和，并以最大计数停止计数。 可以通过寄存器读取操作读取计数器。 第一预定位数和第二预定位数之和为8位的整数倍的总和。

公开(公告)号：US07475172B2

公开(公告)日：2009-01-06

申请号：US11566751

申请日：2006-12-05

申请人： Lewis Nardini ,  Manisha Agarwala ,  John M. Johnsen

发明人： Lewis Nardini ,  Manisha Agarwala ,  John M. Johnsen

IPC分类号： G06F3/00 ,  G06F13/12 ,  G06F9/455 ,  G01R31/28

CPC分类号： G06F11/3636 ,  G06F11/3476

摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.

摘要翻译： 本发明通过将当前跟踪地址的各个字节与存储的先前跟踪地址进行比较来提供跟踪地址压缩。 只有当前跟踪地址中与存储的先前跟踪地址不匹配或者比当前跟踪地址中与存储的先前跟踪地址不匹配的任何部分不太重要的最低有效字节被传送。 这有时会减少需要传输的数据量。 如果存在完全不匹配，则可以使用当前跟踪地址更新先前的跟踪地址。

公开(公告)号：US20070055855A1

公开(公告)日：2007-03-08

申请号：US11359158

申请日：2006-02-21

申请人： Manisha Agarwala ,  Lewis Nardini

发明人： Manisha Agarwala ,  Lewis Nardini

IPC分类号： G06F15/177

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.

公开(公告)号：US07165018B2

公开(公告)日：2007-01-16

申请号：US10301887

申请日：2002-11-22

申请人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

发明人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

IPC分类号： G06F9/455

CPC分类号： G06F11/3648 ,  G01R31/31703 ,  G01R31/31705 ,  G06F11/3656

摘要： An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.

摘要翻译： 存储器访问地址比较器包括将输入存储器访问地址与相应的参考地址进行比较的两个比较器。 比较器根据可选择的标准产生匹配指示，例如地址大小，全部或部分重叠，大于，小于，等于，不等于，小于等于并且大于或等于，并且可以是选择性地 链接。 输入多路复用器允许存储器访问地址总线选择。 比较器输出可以选择性地依赖于相应的数据匹配。 参考地址，比较数据和控制功能通过中央处理单元可访问存储器映射寄存器使能。

公开(公告)号：US20070011662A1

公开(公告)日：2007-01-11

申请号：US11383337

申请日：2006-05-15

申请人： Manisha Agarwala ,  Bryan Thome ,  John Johnsen ,  Gary Swoboda ,  Lewis Nardini ,  Maria Gill

发明人： Manisha Agarwala ,  Bryan Thome ,  John Johnsen ,  Gary Swoboda ,  Lewis Nardini ,  Maria Gill

IPC分类号： G06F9/44

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.

摘要翻译： 在数据处理器中跟踪程序计数器活动的方法周期性地发送包括当前程序计数器地址的程序计数器同步点。 在同步点之间，程序计数器地址由相对于最后一个程序计数器同步点的程序计数器偏移指示。 程序计数器偏移作为整数个预定位数的部分发送。 程序计数器的同步点经常被传送到足够多的程序计数器偏移量至少比程序计数器地址少一个部分。

公开(公告)号：US07117398B2

公开(公告)日：2006-10-03

申请号：US10302192

申请日：2002-11-22

申请人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

发明人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

IPC分类号： G06F11/30 ,  G06F7/02

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

公开(公告)号：US07051197B2

公开(公告)日：2006-05-23

申请号：US10302082

申请日：2002-11-22

申请人： Manisha Agarwala ,  Lewis Nardini

发明人： Manisha Agarwala ,  Lewis Nardini

IPC分类号： G06F11/00

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.

摘要翻译： 一种在数据处理器复位时跟踪数据处理器的方法。 数据处理器复位信号复位数据处理器，跟踪收集硬件的一部分，不会复位跟踪收集硬件的剩余部分。 数据处理器复位信号可以不是由应用程序所拥有或由调试器拥有的。 跟踪收集硬件的部分不复位仅在调试器所拥有的数据处理器复位信号时发生。 跟踪逻辑复位信号在不拥有时复位数据处理器和跟踪收集硬件。 该跟踪逻辑复位信号仅在调试器拥有时复位数据处理器，并在应用程序拥有时重置跟踪收集硬件。