公开(公告)号：US20090138890A1

公开(公告)日：2009-05-28

申请号：US12292565

申请日：2008-11-20

申请人： Geoffrey Blake ,  Trevor Nigel Mudge ,  Stuart David Biles ,  Nathan Yong Seng Chong ,  Emre Ozer ,  Ronald George Dreslinski

发明人： Geoffrey Blake ,  Trevor Nigel Mudge ,  Stuart David Biles ,  Nathan Yong Seng Chong ,  Emre Ozer ,  Ronald George Dreslinski

IPC分类号： G06F9/46

CPC分类号： G06F9/467 ,  G06F9/30087 ,  G06F9/466 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/621

摘要： A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterises previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

公开(公告)号：US09513959B2

公开(公告)日：2016-12-06

申请号：US12149003

申请日：2008-04-24

申请人： Stuart David Biles ,  Geoffrey Blake ,  Trevor Nigel Mudge

发明人： Stuart David Biles ,  Geoffrey Blake ,  Trevor Nigel Mudge

IPC分类号： G06F9/46 ,  G06F9/52 ,  G06F9/48

CPC分类号： G06F9/466 ,  G06F9/467 ,  G06F9/4881 ,  G06F9/528

摘要： A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

摘要翻译： 在具有相关性控制和硬件事务存储器控制电路22的多处理器4,6,8,10系统内提供硬件事务存储器12,14,16,18,20，其用于至少部分地根据处理事务的调度来管理 在冲突数据26,28,30之间。冲突数据表征处理事务之前先前遇到的冲突。 执行调度，使得如果冲突数据指示已经运行的处理事务中的一个先前与候选处理事务冲突，则候选处理事务将不被调度。

公开(公告)号：US20090133032A1

公开(公告)日：2009-05-21

申请号：US12149003

申请日：2008-04-24

申请人： Stuart David Biles ,  Geoffrey Blake ,  Trevor Nigel Mudge

发明人： Stuart David Biles ,  Geoffrey Blake ,  Trevor Nigel Mudge

IPC分类号： G06F9/46

CPC分类号： G06F9/466 ,  G06F9/467 ,  G06F9/4881 ,  G06F9/528

摘要： A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterises previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

摘要翻译： 在具有相关性控制和硬件事务存储器控制电路22的多处理器4,6,8,10系统内提供硬件事务存储器12,14,16,18,20，其用于至少部分地根据处理事务的调度来管理 在冲突数据26,28,30之间。冲突数据表征处理事务之前先前遇到的冲突。 执行调度，使得如果冲突数据指示已经运行的处理事务中的一个先前与候选处理事务冲突，则候选处理事务将不被调度。

公开(公告)号：US08335122B2

公开(公告)日：2012-12-18

申请号：US12292148

申请日：2008-11-12

申请人： Ronald George Dreslinski, Jr. ,  Gregory Kengho Chen ,  Trevor Nigel Mudge ,  David Theodore Blaauw ,  Dennis Sylvester

发明人： Ronald George Dreslinski, Jr. ,  Gregory Kengho Chen ,  Trevor Nigel Mudge ,  David Theodore Blaauw ,  Dennis Sylvester

IPC分类号： G11C5/14

CPC分类号： G06F12/0897 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

摘要： A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.

摘要翻译： 提供一种数据处理装置，其具有包括数据存储阵列和标签阵列的高速缓存存储器，以及响应于来自处理电路执行高速缓存查找的高速缓存访​​问请求而耦合到高速缓冲存储器的高速缓存控制器。 高速缓冲存储器被布置成使得其具有被配置为在第一电压域中操作的第一存储单元组和被配置为在不同于第一电压域的第二电压域中操作的第二存储单元组。 还提供了相应的数据处理方法。

公开(公告)号：US20140019655A1

公开(公告)日：2014-01-16

申请号：US13940915

申请日：2013-07-12

申请人： Supreet Jeloka ,  Sandunmalee Nilmini Abeyratne ,  Ronald George Dreslinski ,  Reetuparna Das ,  Trevor Nigel Mudge ,  David Theodore Blaauw

发明人： Supreet Jeloka ,  Sandunmalee Nilmini Abeyratne ,  Ronald George Dreslinski ,  Reetuparna Das ,  Trevor Nigel Mudge ,  David Theodore Blaauw

IPC分类号： G06F13/374

CPC分类号： G06F13/4022 ,  G06F13/1642 ,  G06F13/374 ,  G06F2213/0038 ,  G11C7/10 ,  G11C7/1012 ,  H03K17/693

摘要： An interconnect 6 within an integrated circuit 2 provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).

摘要翻译： 集成电路2内的互连6提供仲裁以选择用于连接到信号输出的多个信号输入中的一个。 应用的仲裁使用时间戳值形式的第一仲裁参数值，并且如果两个或更多个信号输入共享这样的时间戳值，则使用第二仲裁参数，其形式为最近最近授予的值 。 选择应用于与授予对信号输出的访问时的每个信号输入相关联的时间戳值的时间增量以反映与该信号输入相关联的服务质量。 当在时间戳值之间进行比较时，优先考虑最低时间戳值。 大的时间增量值对应于低优先级（服务质量）。

公开(公告)号：US20090138658A1

公开(公告)日：2009-05-28

申请号：US12292148

申请日：2008-11-12

申请人： Ronald George Dreslinski, JR. ,  Gregory Kengho Chen ,  Trevor Nigel Mudge ,  David Theodore Blaauw ,  Dennis Sylvester

发明人： Ronald George Dreslinski, JR. ,  Gregory Kengho Chen ,  Trevor Nigel Mudge ,  David Theodore Blaauw ,  Dennis Sylvester

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

摘要： A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.

摘要翻译： 提供一种数据处理装置，其具有包括数据存储阵列和标签阵列的高速缓存存储器，以及响应于来自处理电路执行高速缓存查找的高速缓存访​​问请求而耦合到高速缓冲存储器的高速缓存控制器。 高速缓冲存储器被布置成使得其具有被配置为在第一电压域中操作的第一存储单元组和被配置为在不同于第一电压域的第二电压域中操作的第二存储单元组。 还提供了相应的数据处理方法。

公开(公告)号：US08108585B2

公开(公告)日：2012-01-31

申请号：US12379191

申请日：2009-02-13

申请人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester ,  Ronald George Dreslinski, Jr.

发明人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester ,  Ronald George Dreslinski, Jr.

IPC分类号： G06F13/00

CPC分类号： G06F13/4022

摘要： Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a storage circuit programmable to store a routing value, and a transmission circuit. In a transmission mode of operation the transmission circuit is responsive to the routing value indicating that the data input path should be coupled to the data output path to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. Control circuitry is used to issue control signals to the crossbar cells, and during a configuration mode of operation the control circuitry re-utilizes at least one of the data output paths to program the storage circuitry of one or more of the crossbar cells. Such a construction of crossbar circuitry provides a very regular design, with uniform delay across all paths, and which requires significantly less control lines than typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars.

摘要翻译： 交叉开关电路以及这种交叉电路的操作方法。 交叉开关电路具有数据输入路径和数据输出路径的阵列，其中数据输出路径横向于数据输入路径。 在数据输入路径和数据输出路径之间的每个交叉点处，提供包括可编程以存储路由值的存储电路的交叉开关单元和发送电路。 在传输操作模式中，传输电路响应于路由值，该路由值指示数据输入路径应该被耦合到数据输出路径以检测沿着数据输入路径的数据输入，并且输出该数据的指示 相关联的交叉路口的数据输出路径。 控制电路用于向交叉开关单元发出控制信号，并且在配置操作模式期间，控制电路重新利用至少一个数据输出路径来编程一个或多个交叉开关单元的存储电路。 交叉电路电路的这种结构提供非常规则的设计，在所有路径上具有均匀的延迟，并且其需要比典型的现有技术的横杆设计明显更少的控制线。 这种交叉开关电路容易缩放以形成大的横杆。

公开(公告)号：US08650470B2

公开(公告)日：2014-02-11

申请号：US12926084

申请日：2010-10-25

申请人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  David Bull

发明人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  David Bull

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F11/00 ,  G06F11/0706 ,  G06F11/0736 ,  G06F11/0754 ,  G06F11/0757 ,  G06F11/079 ,  G06F11/1402 ,  G06F11/1604

摘要： An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

摘要翻译： 集成电路包括具有错误检测和误差校正电路的一个或多个部分，并且其操作参数给出有限的非零误码率以及形成和操作以提供零错误率的一个或多个部分。

公开(公告)号：US08407537B2

公开(公告)日：2013-03-26

申请号：US12923908

申请日：2010-10-13

申请人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

发明人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

IPC分类号： G06F1/08 ,  G06F11/30

CPC分类号： G06F11/1695 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自 处理逻辑1014处于非延迟捕获时间。 在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟 比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换 值。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

公开(公告)号：US08230277B2

公开(公告)日：2012-07-24

申请号：US13064601

申请日：2011-04-04

申请人： Trevor Nigel Mudge ,  Ganesh Suryanarayan Dasika ,  David Andrew Roberts

发明人： Trevor Nigel Mudge ,  Ganesh Suryanarayan Dasika ,  David Andrew Roberts

IPC分类号： G11C29/00 ,  G06F13/00

CPC分类号： G06F11/1064

摘要： Data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks. A group data store stores data by grouping together blocks that have at least one faulty bit into groups of at least two blocks. For each group of blocks at least one of the blocks has a non-faulty bit for each of the bit locations in the blocks. A selector data store stores indicators for each group indicating which bits of the blocks within a group are the non-faulty bits. When storing data to a data block within a group, the data is stored in each of the blocks within the group. When retrieving data from a data block within a group, the data is read from respective bits of the blocks within the group as indicated by the indicators.

摘要翻译： 数据存储控制电路，用于控制将数据存储在数据块中的数据存储中的数据的存储和检索。 组数据存储器通过将具有至少一个故障位的块组合在一起至少组成两个块来存储数据。 对于每组块，至少一个块具有块中每个位位置的无故障位。 选择器数据存储器存储每个组的指示符，指示组内的块的哪些位是非故障位。 将数据存储到组内的数据块时，将数据存储在组内的每个块中。 当从组内的数据块检索数据时，从指示符指示的组内的块的各个比特中读取数据。