公开(公告)号：US06574725B1

公开(公告)日：2003-06-03

申请号：US09431358

申请日：1999-11-01

申请人： Uwe Kranich ,  David S. Christie

发明人： Uwe Kranich ,  David S. Christie

IPC分类号： G06F940

CPC分类号： G06F9/4843 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885 ,  G06F15/17381

摘要： A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provided. The special coupling mechanism allows it to speculatively execute multiple threads in parallel very efficiently. Generally, the operating system is responsible for scheduling various threads of execution among the available processors in a multiprocessor system. One problem with parallel multithreading is that the overhead involved in scheduling the threads for execution by the operating system is such that shorter segments of code cannot efficiently take advantage of parallel multithreading. Consequently, potential performance gains from parallel multithreading are not attainable. Additional circuitry is included in a form of symmetrical multiprocessing system which enables the scheduling and speculative execution of multiple threads on multiple processors without the involvement and inherent overhead of the operating system. Advantageously, parallel multithreaded execution is more efficient and performance may be improved.

摘要翻译： 提供了一种包含对称多处理系统形式的多个紧密耦合的处理器的处理器架构。 特殊的耦合机制允许它非常有效地推测性地并行地执行多个线程。 通常，操作系统负责在多处理器系统中的可用处理器之间调度各种执行线程。 并行多线程的一个问题是，调度线程以供操作系统执行所涉及的开销使得较短的代码段无法有效地利用并行多线程。 因此，不能实现并行多线程的潜在性能提升。 附加电路包括在对称多处理系统的形式中，其能够在多个处理器上进行多线程的调度和推测执行，而无需操作系统的参与和固有的开销。 有利的是，并行多线程执行更有效率并且可以提高性能。

公开(公告)号：US06456891B1

公开(公告)日：2002-09-24

申请号：US09428614

申请日：1999-10-27

申请人： Uwe Kranich ,  David S. Christie

发明人： Uwe Kranich ,  David S. Christie

IPC分类号： G05B1918

CPC分类号： G06F9/30138 ,  G06F15/7832

摘要： A system and method for transparent handling of extended register states. A set of additional registers, or an extended register file, is added to the base architecture of a microprocessor. The extended register file includes two dedicated registers and a plurality of general-use registers. The extended register file is mapped to a region in main memory. One dedicated register of the extended register file stores the physical base address of the memory region. Another dedicated register of the extended register file is used to store bits to indicate the status of the extended register file. A set of extended instructions is implemented for transferring data to and from the extended register file.

摘要翻译： 一种用于透明处理扩展寄存器状态的系统和方法。 一组附加寄存器或扩展寄存器文件被添加到微处理器的基础架构中。 扩展寄存器文件包括两个专用寄存器和多个通用寄存器。 扩展寄存器文件映射到主存储器中的一个区域。 扩展寄存器文件的一个专用寄存器存储存储器区域的物理基址。 扩展寄存器文件的另一个专用寄存器用于存储位以指示扩展寄存器文件的状态。 实现了一组扩展指令，用于将数据传输到扩展寄存器文件和从扩展寄存器文件传输数据。

公开(公告)号：US6157996A

公开(公告)日：2000-12-05

申请号：US969779

申请日：1997-11-13

申请人： David S. Christie ,  Uwe Kranich

发明人： David S. Christie ,  Uwe Kranich

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38

CPC分类号： G06F9/342 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30138 ,  G06F9/30185

摘要： A processor for executing computer instructions including, in one embodiment, a machine specific register (MSR) which includes a predicated execution field and an instruction decoder. The decoder is coupled to the MSR and configured to detect predicated execution information contained in the computer instruction and to include conditional execution information in the decoded instruction upon detecting an appropriate setting in the predicated execution field of the MSR. The processor further includes a first execution unit. The first execution unit is configured to detect and evaluate the conditional execution information in the decoded instruction and, if present, to execute the decoded instruction only if a condition represented by the conditional execution information is true. In another embodiment, the processor includes a standard register set and an extended register set, which includes the standard register set. The decoder is configured to search the computer instruction for an extended register indicator upon detecting an appropriate setting in the extended register field of the MSR. The decoder is further configured to fetch, upon detecting the extended register indicator, a value from a selected register within the extended register set. If the decoder detects the absence of extended register indicator, a value is fetched from a selected register where the selected register is within the standard register set. In another embodiment, the MSR includes a three register field and the decoder is configured to interpret the computer instruction as containing first and second source register operands and a destination operand if the instruction contains a three register indicator and the three register field is set appropriately.

摘要翻译： 一种用于执行计算机指令的处理器，在一个实施例中包括机器特定寄存器（MSR），其包括预定执行字段和指令解码器。 解码器耦合到MSR，并被配置为检测计算机指令中包含的预测执行信息，并且在检测到MSR的预测执行字段中的适当设置时，将解码指令中的条件执行信息包括在解码指令中。 处理器还包括第一执行单元。 第一执行单元被配置为仅在由条件执行信息表示的条件为真时才检测和评估解码指令中的条件执行信息，并且如果存在则执行解码指令。 在另一实施例中，处理器包括标准寄存器组和扩展寄存器组，其包括标准寄存器组。 解码器被配置为在MSR的扩展寄存器字段中检测到适当的设置时，在计算机指令中搜索扩展寄存器指示符。 解码器还被配置为在检测到扩展寄存器指示符时，从扩展寄存器组内的选定寄存器获取一个值。 如果解码器检测到没有扩展寄存器指示符，则从选定的寄存器中取出一个值，其中所选寄存器在标准寄存器组内。 在另一个实施例中，MSR包括三个寄存器字段，并且解码器被配置为如果指令包含三个寄存器指示符并且三个寄存器字段被适当地设置，则将该计算机指令解释为包含第一和第二源寄存器操作数以及目标操作数。

公开(公告)号：US07012604B1

公开(公告)日：2006-03-14

申请号：US10242199

申请日：2002-09-12

申请人： David S. Christie ,  Uwe Kranich

发明人： David S. Christie ,  Uwe Kranich

IPC分类号： G06T15/60

CPC分类号： G06T15/50 ,  G06T15/06 ,  G06T15/80

摘要： A system and method for generating images of three-dimensional objects. The system includes one or more tracing processors, and one or more shading processors. Each of the tracing processors may be configured to (a) perform a first set of computations on a corresponding group of primary rays emanating from a viewpoint resulting in a ray tree and a set of one or more light trees for each primary ray of the corresponding group, (b) transfer the ray trees and associated light trees to one of the shading processors, and (c) repeat (a) and (b). Each of the shading processors may be configured to (d) receive ray trees and associated light trees from one of the tracing processors, (e) perform a second set of computations on the received ray trees and associated light trees to determine pixel color values, and (f) repeat (d) and (e) a plurality of times.

摘要翻译： 一种用于生成三维物体图像的系统和方法。 系统包括一个或多个跟踪处理器和一个或多个着色处理器。 每个跟踪处理器可以被配置为（a）对从视点发出的对应的一组主线执行第一组计算，得到对应的每个主射线的射线树和一组或多个光树的集合 组，（b）将光线树和相关联的光树转移到阴影处理器之一，以及（c）重复（a）和（b）。 每个阴影处理器可以被配置为（d）从跟踪处理器之一接收射线树和相关联的光树，（e）在接收到的光线树和相关联的光树上执行第二组计算以确定像素颜色值， 和（f）重复（d）和（e）多次。

公开(公告)号：US06651163B1

公开(公告)日：2003-11-18

申请号：US09521248

申请日：2000-03-08

申请人： Uwe Kranich ,  David S. Christie

发明人： Uwe Kranich ,  David S. Christie

IPC分类号： G06F900

CPC分类号： G06F9/3861 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3842 ,  G06F9/3851

摘要： A mechanism for exception and interrupt handling in multithreaded multiprocessors is provided. The mechanism allows the handling of exceptions and interruptions in a multithreaded multiprocessor computer, while hiding the multiprocessor nature of the computer from the operating system. Generally, when an operating system is cognizant of the multiprocessor nature of a computer, additional overhead may be required when handling exceptions and interruptions. Due to the overhead involved in saving and restoring processing states, the performance of a processor may be significantly impacted. Additional circuitry is provided which allows the multiprocessor nature of the computer to be hidden from the operating system, while minimizing the overhead necessary for proper handling.

摘要翻译： 提供了一种用于多线程多处理器中异常和中断处理的机制。 该机制允许在多线程多处理器计算机中处理异常和中断，同时从操作系统隐藏计算机的多处理器性质。 通常，当操作系统识别计算机的多处理器性质时，处理异常和中断时可能需要额外的开销。 由于保存和恢复处理状态所涉及的开销，处理器的性能可能会受到很大的影响。 提供了额外的电路，其允许计算机的多处理器性质从操作系统中隐藏，同时最小化正确处理所需的开销。

公开(公告)号：US06230259B1

公开(公告)日：2001-05-08

申请号：US08961681

申请日：1997-10-31

申请人： David S. Christie ,  Uwe Kranich

发明人： David S. Christie ,  Uwe Kranich

IPC分类号： G06F1500

CPC分类号： G06F9/30138 ,  G06F9/30123 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30189

摘要： A microprocessor having a standard register set and an extended register set, which is configured to save its state upon suspension of either an extended register process or a standard register processor. The microprocessor is configured to execute both standard register instruction sequences and extended register instruction sequences. A first memory is provided for storing a state of the microprocessor when a standard register instruction set sequence is suspended. The microprocessor further comprises a second memory for storing a microprocessor state upon suspension of the microprocessor executing an extended register instruction set sequence. An extended state save circuit coupled between a microprocessor core and the second memory allows the extended state of the microprocessor to be stored without modification of the operating system. As a result, the extended state of the microprocessor can be saved transparently to the operating system.

摘要翻译： 具有标准寄存器组和扩展寄存器组的微处理器，其配置为在暂停扩展寄存器处理或标准寄存器处理器时保存其状态。 微处理器被配置为执行标准寄存器指令序列和扩展寄存器指令序列。 提供第一存储器，用于当暂停标准寄存器指令集序列时存储微处理器的状态。 微处理器还包括第二存储器，用于在执行扩展寄存器指令集序列的微处理器暂停时存储微处理器状态。 耦合在微处理器核心和第二存储器之间的扩展状态保存电路允许在不修改操作系统的情况下存储微处理器的扩展状态。 结果，微处理器的扩展状态可以透明地保存到操作系统。

公开(公告)号：US06185675B2

公开(公告)日：2001-02-06

申请号：US09137579

申请日：1998-08-21

申请人： Uwe Kranich ,  David S. Christie

发明人： Uwe Kranich ,  David S. Christie

IPC分类号： G06F938

CPC分类号： G06F9/3804 ,  G06F9/3806 ,  G06F9/3836

摘要： A cache memory configured to access stored instructions according to basic blocks is disclosed. Basic blocks are natural divisions in instruction streams resulting from branch instructions. The start of a basic block is a target of a branch, and the end is another branch instruction. A microprocessor configured to use a basic block oriented cache may comprise a basic block cache and a basic block sequence buffer. The basic block cache may have a plurality of storage locations configured to store basic blocks. The basic block sequence buffer also has a plurality of storage locations, each configured to store a block sequence entry. The block sequence entry may comprise an address tag and one or more basic block pointers. The address tag corresponds to the fetch address of a particular basic block, and the pointers point to basic blocks that follow the particular basic block in a predicted order. A system using the microprocessor and a method for caching instructions in a block oriented manner rather than conventional power-of-two memory blocks are also disclosed.

摘要翻译： 公开了一种被配置为根据基本块访问存储的指令的高速缓冲存储器。 基本块是由分支指令产生的指令流中的自然分割。 基本块的开始是分支的目标，而结束是另一个分支指令。 配置为使用基于面向块的缓存的微处理器可以包括基本块高速缓存和基本块序列缓冲器。 基本块高速缓存可以具有被配置为存储基本块的多个存储位置。 基本块序列缓冲器还具有多个存储位置，每个存储位置被配置为存储块序列条目。 块序列条目可以包括地址标签和一个或多个基本块指针。 地址标签对应于特定基本块的获取地址，并且指针指向按预测顺序跟随特定基本块的基本块。 还公开了一种使用微处理器的系统和用于以面向块方式缓存指令的方法，而不是传统的二次电力二存储块。

公开(公告)号：US08352688B2

公开(公告)日：2013-01-08

申请号：US12946743

申请日：2010-11-15

申请人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack ,  Luke Yen

发明人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack ,  Luke Yen

IPC分类号： G06F12/00

CPC分类号： G06F12/00 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

摘要： A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.

公开(公告)号：US20120124563A1

公开(公告)日：2012-05-17

申请号：US12947336

申请日：2010-11-16

申请人： Jaewoong Chung ,  Rahmet Ulya Karpuzcu ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack

发明人： Jaewoong Chung ,  Rahmet Ulya Karpuzcu ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack

IPC分类号： G06F9/45

CPC分类号： G06F8/447 ,  G06F9/467

摘要： A method and apparatus for compiling software written to be executed on a microprocessor that supports at least one hardware transactional memory function is provided. A compiler that supports at least one software transactional memory function is adapted to include a runtime system that maps between the at least one software transactional memory function and the at least one hardware transactional memory instruction.

摘要翻译： 提供了一种用于编译写入要在支持至少一个硬件事务存储器功能的微处理器上执行的软件的方法和装置。 支持至少一个软件事务性存储器功能的编译器适于包括在所述至少一个软件事务存储器功能与所述至少一个硬件事务存储器指令之间映射的运行时系统。

公开(公告)号：US20110040906A1

公开(公告)日：2011-02-17

申请号：US12627956

申请日：2009-11-30

申请人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin Pohlack

发明人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin Pohlack

IPC分类号： G06F5/14 ,  G06F12/00

CPC分类号： G06F5/16 ,  G06F9/528

摘要： An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache.

摘要翻译： 一种用于实现具有多级事务缓冲器的硬件事务存储器（HTM）系统的装置，方法和系统。 该装置包括数据高速缓存，其被配置为缓冲由推测性存储器访问操作访问的共享（多个处理核心）存储器中的数据，并且在至少一部分尝试期间保留数据以执行原子存储器事务。 该装置还包括：溢出检测电路，其被配置为在确定数据高速缓冲存储器不足以缓冲作为原子存储器事务的一部分访问的数据的一部分时检测溢出状况，以及配置为响应于检测的缓冲电路 通过防止数据部分被缓冲在数据高速缓冲存储器中并缓冲与数据高速缓存分开的辅助缓冲器中的数据的部分，来实现溢出状态。