公开(公告)号：US20090210656A1

公开(公告)日：2009-08-20

申请号：US12034084

申请日：2008-02-20

申请人： David S. Hutton ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  John G. Rell, JR. ,  Eric M. Schwarz ,  Chung-Lung Kevin Shum

发明人： David S. Hutton ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  John G. Rell, JR. ,  Eric M. Schwarz ,  Chung-Lung Kevin Shum

IPC分类号： G06F15/76 ,  G06F9/02 ,  G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3857 ,  G06F9/3873

摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.

摘要翻译： 提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。 该系统包括在第一执行流水线中执行指令执行的第一执行单元。 该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。 该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行 单元。 该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

公开(公告)号：US07913067B2

公开(公告)日：2011-03-22

申请号：US12034084

申请日：2008-02-20

申请人： David S. Hutton ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  John G. Rell, Jr. ,  Eric M. Schwarz ,  Chung-Lung Kevin Shum

发明人： David S. Hutton ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  John G. Rell, Jr. ,  Eric M. Schwarz ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3857 ,  G06F9/3873

摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.

摘要翻译： 提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。 该系统包括在第一执行流水线中执行指令执行的第一执行单元。 该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。 该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行 单元。 该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

公开(公告)号：US20090240922A1

公开(公告)日：2009-09-24

申请号：US12051792

申请日：2008-03-19

申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

公开(公告)号：US07921279B2

公开(公告)日：2011-04-05

申请号：US12051792

申请日：2008-03-19

申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

公开(公告)号：US07861064B2

公开(公告)日：2010-12-28

申请号：US12037861

申请日：2008-02-26

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung Kevin Shum

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/34 ,  G06F9/38

CPC分类号： G06F9/3826 ,  G06F9/3836

摘要： A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage, determining whether the instruction data can be dispatched to the address generation stage to be processed without being delayed due to an unavailability of a processing resource needed for the processing of the instruction data in the address generation stage, dispatching the instruction data to be processed in the address generation stage if it can be dispatched without being delayed due to the unavailability of the processing resource, and dispatching the instruction data to be processed in the execution stage if it can not be dispatched without being delayed due to the unavailability of the processing resource, wherein the processing of the instruction data is selectively accelerated using an address generation interlock scheme. A corresponding system and computer program product.

摘要翻译： 一种用于选择性地加速早期指令处理的方法，包括接收在处理器流水线的执行阶段中正常处理的指令数据，其中指令数据的配置允许指令数据的处理从执行阶段加速到地址 在处理器流水线中比执行阶段更早发生的生成阶段，确定指令数据是否可以被分派到要处理的地址生成阶段，而不会由于处理指令数据所需的处理资源的不可用而被延迟 地址生成阶段，如果能够由于处理资源的不可用而被分派而不被延迟，则在地址生成阶段调度要处理的指令数据，并且如果不能在执行阶段调度要处理的指令数据 由于你而不被推迟 处理资源的可用性，其中使用地址生成互锁方案选择性地加速指令数据的处理。 相应的系统和计算机程序产品。

公开(公告)号：US07962726B2

公开(公告)日：2011-06-14

申请号：US12051215

申请日：2008-03-19

申请人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

发明人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/00 ,  G06F9/44

CPC分类号： G06F9/30065 ,  G06F9/3832

摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。

公开(公告)号：US20090240914A1

公开(公告)日：2009-09-24

申请号：US12051215

申请日：2008-03-19

申请人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

发明人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/38

CPC分类号： G06F9/30065 ,  G06F9/3832

摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。

公开(公告)号：US07971034B2

公开(公告)日：2011-06-28

申请号：US12051415

申请日：2008-03-19

申请人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

发明人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

IPC分类号： G06F9/00 ,  G06F9/44 ,  G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30076 ,  G06F9/342 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3867

摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.

摘要翻译： 提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。 回收微处理器包括在其上执行的逻辑。 微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。 微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。 在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。 为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

公开(公告)号：US20090240929A1

公开(公告)日：2009-09-24

申请号：US12051415

申请日：2008-03-19

申请人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

发明人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

IPC分类号： G06F9/312

CPC分类号： G06F9/30189 ,  G06F9/30076 ,  G06F9/342 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3867

摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.

摘要翻译： 提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。 回收微处理器包括在其上执行的逻辑。 微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。 微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。 在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。 为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

公开(公告)号：US07975130B2

公开(公告)日：2011-07-05

申请号：US12034042

申请日：2008-02-20

申请人： Khary J. Alexander ,  Fadi Y. Busada ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung Kevin Shum

发明人： Khary J. Alexander ,  Fadi Y. Busada ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/312

CPC分类号： G06F9/3826 ,  G06F9/3016 ,  G06F9/382 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3861

摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.

摘要翻译： 提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。 该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。 该系统还包括监视指令流的延迟逻辑。 延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。 响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。