Method for discarding corrupted data packets in a reliable transport fabric
    1.
    发明授权
    Method for discarding corrupted data packets in a reliable transport fabric 有权
    在可靠的传输结构中丢弃损坏的数据包的方法

    公开(公告)号:US08169908B1

    公开(公告)日:2012-05-01

    申请号:US10905998

    申请日:2005-01-29

    IPC分类号: H04L1/00

    CPC分类号: H04L1/1877 H04L1/0079

    摘要: A method for discarding perpetually-rejected packets in a fabric-based interconnect having a reliable physical layer is disclosed. A transmitting component keeps a count of the number of negative acknowledgements (NAKs) it receives from the receiving component for packets the transmitting component sends. If the transmitting component receives a number of consecutive NAKs for the same packet that exceeds some pre-determined threshold, the packet is not resent, but is, instead, treated as having been acknowledged, and subsequent packets are allowed to be transmitted. Higher-level processes are then notified of the problem so as to allow the error to be dealt with at a higher level, but without obstructing the flow of packets on the physical layer.

    摘要翻译: 公开了一种在具有可靠物理层的基于结构的互连中丢弃永久拒绝的分组的方法。 发送组件保持从发送组件发送的分组的接收组件接收的否定确认数(NAK)的数量。 如果发送组件接收到超过某个预定阈值的相同分组的多个连续NAK,则该分组不重新发送,而是被视为已被确认,并且允许后续分组被发送。 然后,将较高级别的进程通知问题,以便允许在较高级别处理错误,但不会妨碍物理层上的数据包流。

    Adaptive method for training a source synchronous parallel receiver
    2.
    发明申请
    Adaptive method for training a source synchronous parallel receiver 有权
    用于训练源同步并行接收机的自适应方法

    公开(公告)号:US20060268941A1

    公开(公告)日:2006-11-30

    申请号:US11141795

    申请日:2005-05-31

    IPC分类号: H04J3/06

    CPC分类号: H04J3/0629 H04L25/14

    摘要: Disclosed is an adaptive method for training a source synchronous parallel receiver. The adaptive method for training, or aligning, parallel data channels permits a parallel communication receiver to adaptively adjust the timing of data channels to align the data channels with a frame channel and achieve a source synchronous signal for the parallel data channels. Further, portions of the frame channel training pattern may be used because possible time shift accuracy error is accounted for between the communication channels and a determination is made as to which portion of the frame pattern is currently being received. The data channels are then aligned appropriately.

    摘要翻译: 公开了一种用于训练源同步并行接收机的自适应方法。 用于训练或对准并行数据信道的自适应方法允许并行通信接收机自适应地调整数据信道的定时以将数据信道与帧信道对准并且实现并行数据信道的源同步信号。 此外,可以使用帧信道训练模式的部分,因为在通信信道之间考虑到可能的时移精度误差,并且确定当前正在接收帧模式的哪个部分。 然后数据通道适当地对齐。

    Adaptive elasticity FIFO
    3.
    发明申请
    Adaptive elasticity FIFO 失效
    自适应弹性FIFO

    公开(公告)号:US20070002991A1

    公开(公告)日:2007-01-04

    申请号:US11157270

    申请日:2005-06-20

    IPC分类号: H04L7/00

    CPC分类号: H04L7/02 H04J3/0632

    摘要: Disclosed is a method for minimizing the buffer size of an elasticity FIFO queue when synchronizing data between two clock domains. Data communication is typically sent by a transmitter device to a receiver device. The transmitted data signal includes an embedded clock signal and null data characters, as specified by the data communication signal protocol. A null character indicates an empty data frame and is included as part of most standard communication protocols. An embodiment skips one or more null characters from the elasticity FIFO queue during a single clock cycle when it is detected that the write pointer is catching up to the read pointer. By skipping multiple null characters during a single write cycle, the read pointer is moved ahead by one or more queue locations and the write pointer is insured to not catch up to the read pointer for a wider variation in frequencies between a transmitter and receiver than is normally possible. Typically, the elasticity FIFO queue size must be increased in order to support a larger frequency variation. By reducing the need to increase the elasticity FIFO queue size, the gate count and area needed for the elasticity FIFO queue on the silicon chip of the receiver is reduced, thus, reducing the cost contribution of the elasticity FIFO queue to the receiver device. Skipping null characters also reduces the latency time between a write and the associated read of a non-null data character.

    摘要翻译: 公开了一种在两个时钟域之间同步数据时最小化弹性FIFO队列的缓冲器大小的方法。 数据通信通常由发射机设备发送到接收机设备。 传输的数据信号包括嵌入的时钟信号和数据通信信号协议规定的空数据字符。 空字符表示空数据帧,并且被包括为大多数标准通信协议的一部分。 当检测到写指针正在赶上读指针时,实施例在单个时钟周期期间从弹性FIFO队列跳过一个或多个空字符。 通过在单个写入周期期间跳过多个空字符,读取指针向前移动一个或多个队列位置,并且写入指针被保险以避免发送器和接收器之间的频率更宽的变化的读指针 通常可能的 通常,为了支持更大的频率变化,必须增加弹性FIFO队列的大小。 通过减少增加弹性FIFO队列大小的需要,降低了接收机硅芯片上的弹性FIFO队列所需的门数和面积,从而降低了弹性FIFO队列对接收机设备的成本贡献。 跳过空字符也减少了写入和非空数据字符的关联读取之间的等待时间。

    Method for reducing latency
    4.
    发明申请
    Method for reducing latency 有权
    降低延迟的方法

    公开(公告)号:US20060277329A1

    公开(公告)日:2006-12-07

    申请号:US11147855

    申请日:2005-06-07

    IPC分类号: G06F3/00

    摘要: Disclosed is a method for reducing latency between two clock domains in a digital electronic device. The time between a write to a queue position and a corresponding read of the queue position is reduced by up to one clock cycle by including a delay in the time before first writing data to a First In First Out (FIFO) queue used to buffer and synchronize data between two clock domains. The two clock domains have the same frequency, but may be out of phase. Reducing the latency between the write and the corresponding read reduces the required size of the FIFO queue and also results in more efficient system operation.

    摘要翻译: 公开了一种用于减少数字电子设备中的两个时钟域之间的等待时间的方法。 在写入队列位置和队列位置的对应读取之间的时间通过在首先将数据写入到用于缓冲的先入先出(FIFO))队列之前的时间中包括延迟来减少最多一个时钟周期,并且 在两个时钟域之间同步数据。 两个时钟域具有相同的频率,但是可能不同步。 减少写入和相应读取之间的延迟可以减少FIFO队列所需的大小,并且还可以实现更有效的系统操作。

    Page boundary detector
    5.
    发明申请
    Page boundary detector 失效
    页边界检测器

    公开(公告)号:US20050086595A1

    公开(公告)日:2005-04-21

    申请号:US10687991

    申请日:2003-10-17

    IPC分类号: G06F15/00 G11C7/10 G11C8/00

    CPC分类号: G11C8/00 G11C7/1018

    摘要: A logical gate and a comparator are used to detect page boundaries in a data stream. A current address and a predetermined page size, that is an integer power of 2, are compared using a Boolean logic gate such as AND or XOR to detect a page boundary in a data stream. The output from the Boolean logic gate is compared to a predetermined value to cause a signal to be generated, indicating the end of the page.

    摘要翻译: 逻辑门和比较器用于检测数据流中的页边界。 使用诸如AND或XOR之类的布尔逻辑门来比较当前地址和预定的页大小,即2的整数幂,以检测数据流中的页边界。 将来自布尔逻辑门的输出与预定值进行比较,以产生指示页面结束的信号。

    AUTOMATED HIGH PERFORMANCE WAVEFORM DESIGN BY EVOLUTIONARY ALGORITHM
    7.
    发明申请
    AUTOMATED HIGH PERFORMANCE WAVEFORM DESIGN BY EVOLUTIONARY ALGORITHM 有权
    自动化的高性能波形设计通过演化算法

    公开(公告)号:US20140035992A1

    公开(公告)日:2014-02-06

    申请号:US13563445

    申请日:2012-07-31

    IPC分类号: B41J29/393

    摘要: A method can include receiving an initial waveform and generating, testing, and evaluating the performance of an initial child set of waveforms based on an initial parent set of waveforms from the initial waveform. The method can also include determining whether a termination condition has been met based on the evaluating and, if so, providing an optimized waveform. If the termination condition has not been met, the method can also include generating subsequent child sets of waveforms based on the previous child set(s).

    摘要翻译: 一种方法可以包括基于来自初始波形的初始父组波形来接收初始波形并生成,测试和评估初始子波形组的性能。 该方法还可以包括基于评估来确定是否满足终止条件,并且如果是,则提供优化的波形。 如果没有满足终止条件,则该方法还可以包括基于先前的子组来生成后续的子组波形。

    HOME NETWORK OF CONNECTED CONSUMER DEVICES
    8.
    发明申请
    HOME NETWORK OF CONNECTED CONSUMER DEVICES 审中-公开
    连接消费者设备的家庭网络

    公开(公告)号:US20140025805A1

    公开(公告)日:2014-01-23

    申请号:US13551562

    申请日:2012-07-17

    IPC分类号: G06F15/173

    摘要: A method of generating a representation of a structure includes providing an ad hoc mesh network having at least two nodes associated with the structure, obtaining time of flight data for each node in the network, and using the time of flight data to generate the representation of the structure. A method of generating a three-dimensional representation of a structure includes providing an ad hoc mesh network having at least three nodes associated with the structure, wherein at least one node is a mobile node that moves around the structure, obtaining time of flight data for each pair of nodes in the network, and using the time of flight data to generate the three-dimensional representation of the structure.

    摘要翻译: 一种产生结构表示的方法包括:提供具有与所述结构相关联的至少两个节点的自组织网格网络,获得所述网络中每个节点的飞行时间数据,以及使用所述飞行时间数据来生成 结构。 一种生成结构的三维表示的方法包括:提供具有与所述结构相关联的至少三个节点的自组织网格网络,其中至少一个节点是围绕所述结构移动的移动节点,获得用于 网络中的每对节点,并使用飞行时间数据来生成结构的三维表示。

    Automated high performance waveform design by evolutionary algorithm
    9.
    发明授权
    Automated high performance waveform design by evolutionary algorithm 有权
    通过进化算法自动化的高性能波形设计

    公开(公告)号:US09289976B2

    公开(公告)日:2016-03-22

    申请号:US13563445

    申请日:2012-07-31

    IPC分类号: B41J29/393 B41J2/045

    摘要: A method can include receiving an initial waveform and generating, testing, and evaluating the performance of an initial child set of waveforms based on an initial parent set of waveforms from the initial waveform. The method can also include determining whether a termination condition has been met based on the evaluating and, if so, providing an optimized waveform. If the termination condition has not been met, the method can also include generating subsequent child sets of waveforms based on the previous child set(s).

    摘要翻译: 一种方法可以包括基于来自初始波形的初始父组波形来接收初始波形并生成,测试和评估初始子波形组的性能。 该方法还可以包括基于评估来确定是否满足终止条件,并且如果是,则提供优化的波形。 如果没有满足终止条件,则该方法还可以包括基于先前的子组来生成后续的子组波形。