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公开(公告)号：US10394998B2
公开(公告)日：2019-08-27
申请号：US13401922
申请日：2012-02-22
IPC分类号： G06F17/50
摘要： Embodiments of the present invention provide a system, method, and program product for accelerating a simulated memory walking sequence during a simulation conducted by a computer. In one embodiment, a simulation test-case is executed and one or more memory locations in the simulated memory are identified as eligible to contain valid data. Subsequent to commencement of the simulated memory walking sequence, it is determined whether an identified memory location is within a specified number of memory locations after a memory location to be processed by simulated hardware during the simulated memory walking sequence. If an identified memory location is within the specified number, the simulated hardware is allowed to process the memory location. If an identified memory location is not within the specified number, the simulated hardware is advanced to a subsequent memory location and is allowed to process the subsequent memory location.
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公开(公告)号：US20130218550A1
公开(公告)日：2013-08-22
申请号：US13401922
申请日：2012-02-22
IPC分类号： G06F21/00
CPC分类号： G06F17/5081
摘要： Embodiments of the present invention provide a system, method, and program product for accelerating a simulated memory walking sequence during a simulation conducted by a computer. In one embodiment, a simulation test-case is executed and one or more memory locations in the simulated memory are identified as eligible to contain valid data. Subsequent to commencement of the simulated memory walking sequence, it is determined whether an identified memory location is within a specified number of memory locations after a memory location to be processed by simulated hardware during the simulated memory walking sequence. If an identified memory location is within the specified number, the simulated hardware is allowed to process the memory location. If an identified memory location is not within the specified number, the simulated hardware is advanced to a subsequent memory location and is allowed to process the subsequent memory location.
摘要翻译： 本发明的实施例提供了一种用于在由计算机执行的模拟期间加速模拟存储器行走序列的系统，方法和程序产品。 在一个实施例中，执行模拟测试情况，并且模拟存储器中的一个或多个存储器位置被识别为包含有效数据的资格。 在模拟存储器步行序列开始之后，在模拟的存储器行走序列期间，在被模拟硬件处理的存储器位置之后，确定所识别的存储器位置是否在指定数量的存储器位置内。 如果识别的存储器位置在指定的数量内，则允许模拟硬件处理存储器位置。 如果识别的存储器位置不在指定的数量内，则模拟的硬件被提前到后续存储器位置，并被允许处理随后的存储器位置。
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公开(公告)号：US08117390B2
公开(公告)日：2012-02-14
申请号：US12424434
申请日：2009-04-15
申请人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0822 , G06F12/0897 , G06F2212/507
摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
摘要翻译： 用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。 处理单元还包括耦合到并支持处理器核的多级高速缓存层级。 多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。 响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送至至少一个上级高速缓冲存储器来服务存储器访问请求。 至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。
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4.发明授权Barriers processing in a multiprocessor system having a weakly ordered storage architecture without broadcast of a synchronizing operation 失效在具有弱排序存储体系结构的多处理器系统中进行障碍处理，而无需广播同步操作公开(公告)号：US08095739B2
公开(公告)日：2012-01-10
申请号：US12422698
申请日：2009-04-13
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F12/0815 , G06F12/0862 , G06F12/126
摘要： A data processing system employing a weakly ordered storage architecture includes first and second sets of processing units coupled to each other and data storage by an interconnect fabric. Each processing unit has a processor core having an associated cache hierarchy including at least a level one, level two and level three cache memories. A request to perform an update to a portion of a first image of memory contained in the level three cache memory of a first processing unit while at last one kill-type command is pending at the first processing unit, the cache hierarchy of the first processing unit permitting the update to be exposed to any first processor core only after the at least one kill-type command is complete.
摘要翻译： 采用弱有序存储架构的数据处理系统包括彼此耦合的第一和第二组处理单元以及互连结构的数据存储。 每个处理单元具有处理器核心，其具有包括至少一级，二级和三级高速缓冲存储器的相关联的高速缓存层级。 在最后一个杀死型命令时，对包含在第一处理单元的三级高速缓冲存储器中的存储器的第一图像的一部分进行更新的请求在第一处理单元处于等待状态，第一处理的高速缓存层级 单元允许仅在至少一个杀死型命令完成之后将更新暴露给任何第一处理器核。
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5.发明申请Barriers Processing in a Multiprocessor System Having a Weakly Ordered Storage Architecture Without Broadcast of a Synchronizing Operation 失效具有弱序列存储架构的多处理器系统中的障碍处理，无需广播同步操作公开(公告)号：US20100262786A1
公开(公告)日：2010-10-14
申请号：US12422698
申请日：2009-04-13
CPC分类号： G06F12/0897 , G06F12/0815 , G06F12/0862 , G06F12/126
摘要： A data processing system employing a weakly ordered storage architecture includes first and second sets of processing units coupled to each other and data storage by an interconnect fabric. Each processing unit has a processor core having an associated cache hierarchy including at least a level one, level two and level three cache memories. In response to a request to perform an update to a portion of a first image of memory contained in the level three cache memory of a first processing unit while at last one kill-type command is pending at the first processing unit, the cache hierarchy of the first processing unit permitting the update to be exposed to any first processor core only after the at least one kill-type command is complete.
摘要翻译： 采用弱有序存储架构的数据处理系统包括彼此耦合的第一和第二组处理单元以及互连结构的数据存储。 每个处理单元具有处理器核心，其具有包括至少一级，二级和三级高速缓冲存储器的相关联的高速缓存层级。 响应于对包含在第一处理单元的三级高速缓冲存储器中的存储器的第一图像的一部分执行更新的请求，而最后一个杀死型命令在第一处理单元处于等待状态，则高速缓存层级 所述第一处理单元仅在所述至少一个杀死型命令完成之后允许所述更新暴露于任何第一处理器核心。
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公开(公告)号：US20100268884A1
公开(公告)日：2010-10-21
申请号：US12424434
申请日：2009-04-15
申请人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
CPC分类号： G06F12/0822 , G06F12/0897 , G06F2212/507
摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
摘要翻译： 用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。 处理单元还包括耦合到并支持处理器核的多级高速缓存层级。 多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。 响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送到至少一个上级高速缓冲存储器以服务存储器访问请求。 至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。
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公开(公告)号：US06186575B1
公开(公告)日：2001-02-13
申请号：US09330721
申请日：1999-06-11
IPC分类号： B60P702
CPC分类号： B62D47/003
摘要： A re-configurable cargo cover for a bed of a vehicle includes a door adapted to be disposed in a door opening of a vehicle body. The re-configurable cargo cover includes a plurality of individual panels operatively cooperating with each other and a bed of a vehicle. The re-configurable cargo cover includes a pair of interior sides operatively connected to sides of the bed of the vehicle. The re-configurable cargo cover further includes the panels and the sides having features cooperating with each other to re-configure the panels into a plurality of different configurations for a cargo area of the bed of the vehicle.
摘要翻译： 用于车辆的床的可重新配置的货物盖包括适于设置在车体的门开口中的门。 可重新配置的货物盖包括彼此操作地配合的多个单独的面板和车辆的床。 可重新配置的货物盖包括可操作地连接到车辆的床的侧面的一对内侧。 可重新配置的货舱盖还包括面板，并且侧面具有彼此配合的特征，以将面板重新配置成用于车辆床的货物区域的多种不同配置。
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公开(公告)号：US20130332137A1
公开(公告)日：2013-12-12
申请号：US13492399
申请日：2012-06-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022 , G06F17/5031 , G06F2217/84
摘要： A computer identifies a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced. In response to identifying the storage element, an indication of the storage element and the associated clock signal are stored in a database. In response to receiving an input indicating the value of the storage element is to be forced during simulation, a determination is made by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal. In response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, an indication that forcing of the value is mistimed is output.
摘要翻译： 计算机在集成电路设计的仿真模型中识别存储元件，其在使用仿真模型的集成电路设计的仿真期间被迫使其值被强制。 响应于识别存储元件，将存储元件和相关联的时钟信号的指示存储在数据库中。 响应于接收到在模拟期间指示存储元件的值的输入，通过参考数据库来确定参考相关联的时钟信号是否使该值的强制失效。 响应于参考相关联的时钟信号来确定输入值所表示的值的强制被确定，输出该值的强制被指示的指示。
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