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1.发明授权Apparatus for coordinating clock oscillators in a fully redundant computer system 失效用于在全冗余计算机系统中协调时钟振荡器的装置
公开(公告)号：US5812822A
公开(公告)日：1998-09-22
申请号：US574821
申请日：1995-12-19
CPC分类号： G06F11/1679 , G06F1/12
摘要： A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the oscillator signal generated by its own CGD unit. When the two systems are merged, one oscillator is designated as master, and its output is employed to derive the clock and definer signals on both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local oscillator signal, which is in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level. The hold continues until the oscillator which is to "take over" is also at the predetermined logic level.
摘要翻译： 包括能够独立运行的两个系统的冗余计算机系统。 两个系统相应地采用两个独立的时钟产生和分配（CGD）单元，每个单元发出时钟和时钟定义信号。 当两个系统分离时，每个系统由其自己的CGD单元产生的振荡器信号控制。 当两个系统合并时，一个振荡器被指定为主机，并且其输出用于在冗余系统的两侧导出时钟和定义信号。 每个CGD单元中包含的特殊逻辑可确保从主机到从机（或从机）到主机的运行无变化。 该特殊逻辑包括当本地时钟和定义信号都处于预定的逻辑电平时，将本地振荡器信号暂时保持在预定逻辑电平上的电路，该本地振荡器信号在开关被使用时使用。 保持持续，直到“接管”的振荡器也处于预定的逻辑电平。
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2.发明授权Apparatus for coordinating clock distribution in a fully redundant computer system 失效用于在完全冗余的计算机系统中协调时钟分配的装置
公开(公告)号：US5745742A
公开(公告)日：1998-04-28
申请号：US574804
申请日：1995-12-19
CPC分类号： G06F1/12
摘要： A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the clock and definer signals generated by its own CGD unit. When the two systems are merged, one CGD unit is designated as master, and its clock and definer signals drives both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local clock and definer signals, which are in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level. The hold continues until the clock and definer signals which are to "take over" are also at the predetermined logic level.
摘要翻译： 包括能够独立运行的两个系统的冗余计算机系统。 两个系统相应地采用两个独立的时钟产生和分配（CGD）单元，每个单元发出时钟和时钟定义信号。 当两个系统分离时，每个系统由其自己的CGD单元产生的时钟和定义信号控制。 当两个系统合并时，一个CGD单元被指定为主机，其时钟和定义信号驱动冗余系统的两侧。 每个CGD单元中包含的特殊逻辑可确保从主机到从机（或从机）到主机的运行无变化。 该特殊逻辑包括当本地时钟和定义信号均处于预定逻辑电平时，在本地时钟和定义信号上暂时保持暂时保持，这些信号在开关被使用时正在使用。 保持继续，直到要“接管”的时钟和定义信号也处于预定的逻辑电平。
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公开(公告)号：US5740350A
公开(公告)日：1998-04-14
申请号：US823663
申请日：1997-03-18
CPC分类号： G06F13/4269 , G06F11/1423 , G06F11/2028 , G06F11/2038 , G06F15/8007
摘要： A reconfigurable computer system which includes two computer subsystems, corresponding lines of the system busses of the two computer subsystems being interconnected by solid state switches. Each of the computer subsystems includes a control component, a service processor, which when an error is detected that would render the subsystem inoperative, causes the solid state switches to open to sever the connection between the system busses of the two computer subsystems so that the computer subsystem that has not suffered such a failure can continue to operate. A communication link is also established between the two service processors. Either, or both, service processors can sever the link between them.
摘要翻译： 一种可重构计算机系统，其包括两个计算机子系统，两个计算机子系统的系统总线的对应线路由固态开关互连。 每个计算机子系统包括控制组件，服务处理器，当检测到错误以使子系统不起作用时，导致固态开关断开以断开两个计算机子系统的系统总线之间的连接，使得 没有遭受这种故障的计算机子系统可以继续运行。 在两个服务处理器之间也建立通信链路。 服务处理器或者两者都可以切断它们之间的链接。
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4.发明授权Apparatus for phase synchronizing clock signals in a fully redundant computer system 失效用于在完全冗余的计算机系统中相位同步时钟信号的装置
公开(公告)号：US6055362A
公开(公告)日：2000-04-25
申请号：US625664
申请日：1996-03-29
CPC分类号： G06F11/1679 , G06F1/12
摘要： A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. The clock and definer signals of each system are used internally and are also sent to the other system. When the two systems are split, phase locked loops in each system are disabled, and each system is controlled by a precision oscillator in its own CGD unit When the two systems are merged, one CGD is designated as master and remains under control of its internal oscillator. The clock and definer signals of the master system are employed in the slave system to derive a signal which is used as the reference input to the slave system's phase locked loop from which the slave system's clock and definer signals are developed. Preferably, dual flip-flop phase detector type phase locked loops are employed. For higher frequency operation, it is desirable to incorporate certain correction circuitry which minimizes phase offset at apparent phase lock which is an inherent characteristic of this type of phase locked loop.
摘要翻译： 包括能够独立运行的两个系统的冗余计算机系统。 两个系统相应地采用两个独立的时钟产生和分配（CGD）单元，每个单元发出时钟和时钟定义信号。 每个系统的时钟和定义信号在内部使用，并被发送到另一个系统。 当两个系统分裂时，每个系统中的锁相环被禁用，并且每个系统由其自己的CGD单元中的精密振荡器控制。当两个系统合并时，一个CGD被指定为主机并保持在其内部的控制下 振荡器 在从系统中采用主系统的时钟和定义信号来导出一个信号，该信号用作从系统的锁相环的参考输入，从系统的时钟和定义信号开始。 优选地，采用双触发器相位检测器型锁相环。 对于较高频率的操作，期望结合某些校正电路，该校正电路将相位偏移最小化，该视差锁相是这种类型的锁相环的固有特性。
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5.发明授权Method and apparatus for increasing the speed of data exchange among the subsystems of a data processing system 失效用于提高数据处理系统的子系统之间的数据交换速度的方法和装置
公开(公告)号：US5583998A
公开(公告)日：1996-12-10
申请号：US9366
申请日：1993-01-26
申请人： David A. Bowman
发明人： David A. Bowman
CPC分类号： G06F13/409
摘要： In order to increase the information exchange speed among the several transaction members or subsystems organized around a bus carried on a backpanel, all lines of the bus are isolated, using CMOS switches, from the stub to each transaction member which is not instantaneously required for information exchange. The CMOS switches are physically placed as close as practical to the junction of each individual stub to the bus proper. This is achieved by placing the integrated circuits containing the CMOS switches on each subsystem circuit board proximate the male-edge-connector-to-female-edge-connector regions at which the junctions between the bus proper and the stubs are established. Preferably, the CMOS switch integrated circuits are emplaced on the backpanel itself proximate the edge connector regions communicating with each of the subsystems.
摘要翻译： 为了增加在背板上运行的总线上组织的几个交易成员或子系统之间的信息交换速度，总线的所有线路都使用CMOS开关从存根隔离到每个交易成员，而不是立即需要信息 交换。 CMOS开关实际上被放置得尽可能靠近每个单独插脚到总线本体的连接处。 这是通过将包含CMOS开关的集成电路放置在靠近总线适配器和存根之间的连接点的公边连接器到母边缘连接器区域的每个子系统电路板上来实现的。 优选地，CMOS开关集成电路本身靠近与每个子系统通信的边缘连接器区域放置在背板本身上。
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6.发明授权
公开(公告)号：US5642901A
公开(公告)日：1997-07-01
申请号：US509993
申请日：1995-08-01
申请人： David A. Bowman , David J. Davis
发明人： David A. Bowman , David J. Davis
IPC分类号： B60Q1/00 , B60Q5/00 , B60R21/2165 , B60R21/20
CPC分类号： B60R21/21658 , B60Q1/0082 , B60Q5/003 , H01H2223/003
摘要： A relatively flexible thermoplastic air bag cover is provided including a front panel wherein switch activating members enhance activation of a membrane-type switch located at a switch location area of the front panel. This feature provides pressure points which enhance activation of the membrane-type switch. The switch activating members are located on the rear inner surface of the cover in one embodiment and, in another embodiment, on the upper surface of a back plate which provides a hollow compartment for the switch. The switch activating members can be integrally formed in the shape of small circles, ribs, raised dots, X's, etc.
摘要翻译： 提供了一种相对柔性的热塑性气囊盖，其包括前面板，其中开关致动构件增强位于前面板的开关位置区域处的膜型开关的活化。 该功能提供了增强膜式开关激活的压力点。 在一个实施例中，开关致动构件位于盖的后内表面上，并且在另一实施例中，位于提供用于开关的中空隔室的背板的上表面上。 开关激活构件可以一体地形成为小圆形，肋状，凸点，X等的形状
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公开(公告)号：US4006467A
公开(公告)日：1977-02-01
申请号：US632127
申请日：1975-11-14
申请人： David A. Bowman
发明人： David A. Bowman
IPC分类号： G06F11/10 , G11C11/407 , G11C11/4076 , G11C11/40
CPC分类号： G06F11/1028 , G11C11/407 , G11C11/4076
摘要： A memory organization system is disclosed which comprises an improved, bit-organized RAM system. The invention substantially limits errors within the RAM system such that they are error-correctible by existing error detection and correction means. Commonly available RAMs are organized on a logic board such that each bit of a word being addressed is provided by a different RAM chip and is driven by a distinct driver. In this manner a malfunction in either a chip or a driver circuit results in only a one-bit error per word and overall system performance is also improved.
摘要翻译： 公开了一种存储器组织系统，其包括改进的位组织RAM系统。 本发明基本上限制了RAM系统内的错误，使得它们由现有的错误检测和校正装置可纠错。 通常可用的RAM被组织在逻辑板上，使得被寻址的单词的每个位由不同的RAM芯片提供，并由不同的驱动器驱动。 以这种方式，芯片或驱动器电路中的故障仅导致每个字的一位错误，并且整体系统性能也得到改善。
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