Polysilicon coated swami (sidewall masked isolation)
    3.
    发明授权
    Polysilicon coated swami (sidewall masked isolation) 失效
    多晶硅涂层swami(侧壁屏蔽隔离)

    公开(公告)号:US5976950A

    公开(公告)日:1999-11-02

    申请号:US119865

    申请日:1998-07-21

    IPC分类号: H01L21/762 H01L21/76

    CPC分类号: H01L21/76205 H01L21/76232

    摘要: A side wall masked isolation (SWAMI) technique for isolating active regions on an integrated circuit involves reducing the "bird's beak" structure. The technique involves forming an isolation recess in the substrate, and then lining the recess with a layer of silicon dioxide, and then a layer of silicon nitride. Then, oxide spacers are formed on each of the sidewalls of the recess. The recess is then anisotropically etched until the substrate at the bottom of the recess is exposed. This etch process involves removing portion of both the silicon dioxide and the silicon nitride layers formed at the bottom of the recess. Subsequently, a layer of polycrystalline silicon material is deposited in the recess and is then etched back and oxidized to form a field oxide. Since the polycrystalline silicon is oxidized, the result is negligible oxide encroachment resulting in a reduction in the "bird's beak" structure.

    摘要翻译: 用于隔离集成电路上的有源区域的侧壁屏蔽隔离(SWAMI)技术包括减少“鸟嘴”结构。 该技术涉及在衬底中形成隔离凹槽,然后用一层二氧化硅衬垫该凹槽,然后是一层氮化硅。 然后,在凹部的每个侧壁上形成氧化物间隔物。 然后将凹陷进行各向异性蚀刻,直到凹部底部的基板露出。 该蚀刻工艺涉及去除在凹陷底部形成的二氧化硅和氮化硅层的部分。 随后,在凹槽中沉积一层多晶硅材料,然后将其回蚀并氧化以形成场氧化物。 由于多晶硅被氧化,结果是可忽略的氧化物侵蚀导致“鸟的喙”结构的减少。

    Method and system for predictive multi-component circuit layout generation with reduced design cycle
    7.
    发明授权
    Method and system for predictive multi-component circuit layout generation with reduced design cycle 有权
    具有减少设计周期的预测多组件电路布局生成方法和系统

    公开(公告)号:US06839887B1

    公开(公告)日:2005-01-04

    申请号:US10029476

    申请日:2001-10-24

    IPC分类号: G06F9/45 G06F9/455 G06F17/50

    CPC分类号: G06F17/5063

    摘要: One embodiment discloses receiving a number of parameter values for a multi-component circuit. From the received parameter values, a number of parasitic values for various components in the multi-component circuit are determined. For example, parasitic resistor values and parasitic capacitor values for transistors in the multi-component circuit are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the multi-component circuit. According to a disclosed embodiment, a layout of the multi-component circuit is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the multi-component circuit. As such, the parasitic values of the multi-component circuit have already been taken into account in the initial circuit simulation and there is no need to extract the internal parasitics of the multi-component circuit for further circuit simulations.

    摘要翻译: 一个实施例公开了接收多组件电路的多个参数值。 从接收到的参数值中,确定多组分电路中的各种组件的寄生值的数量。 例如,确定多组分电路中的晶体管的寄生电阻值和寄生电容值。 寄生电阻值和寄生电容值用于模拟多分量电路。 根据所公开的实施例,然后产生多分量电路的布局,其导致与模拟多分量电路中已经使用的寄生值相同的寄生值。 因此,在初始电路仿真中已经考虑了多分量电路的寄生值,并且不需要提取用于进一步电路仿真的多分量电路的内部寄生效应。

    Method and system for predictive MOSFET layout generation with reduced design cycle
    8.
    发明授权
    Method and system for predictive MOSFET layout generation with reduced design cycle 有权
    减少设计周期的预测MOSFET布局生成方法和系统

    公开(公告)号:US06728942B2

    公开(公告)日:2004-04-27

    申请号:US09879142

    申请日:2001-06-12

    IPC分类号: G06F1750

    CPC分类号: G06F17/5068

    摘要: In one disclosed embodiment, a number of parameter values for an RF MOSFET are received. Examples of parameter values are style, bulk contact, finger width, finger length, number of fingers, current, and slice parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the RF MOSFET are determined. For example, parasitic resistor values and parasitic capacitor values of the RF MOSFET are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the RF MOSFET. An RF MOSFET layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the RF MOSFET. As such, the parasitic values of the RF MOSFET have already been taken into account in the initial circuit simulation.

    摘要翻译: 在一个公开的实施例中,接收RF MOSFET的多个参数值。 参数值的示例是样式,批量接触,手指宽度,手指长度,手指数,当前和切片参数值。 根据接收的参数值,确定RF MOSFET的子电路模型的寄生数值。 例如,确定RF MOSFET的寄生电阻值和寄生电容值。 寄生电阻值和寄生电容值用于模拟包括RF MOSFET的电路。 然后产生RF MOSFET布局,其导致寄生值与在模拟包括RF MOSFET的电路中已经使用的寄生值相同。 因此,在初始电路仿真中已经考虑了RF MOSFET的寄生值。

    Ground joint coupling having a polymeric seat
    9.
    发明授权
    Ground joint coupling having a polymeric seat 失效
    具有聚合座的接地联轴器

    公开(公告)号:US5577777A

    公开(公告)日:1996-11-26

    申请号:US335558

    申请日:1994-11-07

    CPC分类号: F16L19/0212

    摘要: A ground joint coupling for hoses comprises a stem, a ground joint head formed at a first end portion of the stem, a spud having a first end portion, a molded polymeric annular seat adapted to be positioned between the ground joint head of the stem and the first end portion of the spud, and a nut for connecting the stem to the spud and for compressing the seat between the ground joint head of the stem and the first end portion of the spud. The seat may be made of polytetrafluoroethylene, ultra high molecular weight polyethylene, polyetheretherketone compounds, polyphenylene sulfide compounds, fluoroplastic compounds, or acetal compounds, and the seat may include a filler, such as glass, moly, carbon, bronze, graphite, calcium fluoride, polyphenoline-sulfide, ceramics, silica-based minerals, or combinations thereof.

    摘要翻译: 用于软管的地面接头连接件包括杆,形成在杆的第一端部处的接头头部,具有第一端部部分的模制聚合物环形座,适于定位在杆的地面接头头部和 所述立柱的所述第一端部以及用于将所述杆连接到所述突出部并且用于压缩所述杆的地面接头头部与所述立柱的所述第一端部之间的所述座椅的螺母。 座椅可以由聚四氟乙烯,超高分子量聚乙烯,聚醚醚酮化合物,聚苯硫醚化合物,氟塑料化合物或缩醛化合物制成,并且该座可以包括填料如玻璃,钼,碳,青铜,石墨,氟化钙 ,多元酚硫化物,陶瓷,二氧化硅基矿物或其组合。