公开(公告)号：US5241223A

公开(公告)日：1993-08-31

申请号：US881592

申请日：1992-05-12

申请人： Dennis C. Banker ,  Jack A. Dorler ,  Paul D. Hendricks ,  Frank M. Masci ,  Stephen J. Tytran

发明人： Dennis C. Banker ,  Jack A. Dorler ,  Paul D. Hendricks ,  Frank M. Masci ,  Stephen J. Tytran

IPC分类号： H03K19/003 ,  H03K19/086

CPC分类号： H03K19/00376 ,  H03K19/086

摘要： NOR logic performed by a half current switch emitter follower ("HCSEF") circuit utilizing a transistor operated in the inverse active mode as its current source and having logic levels compatible with those of current switch emitter follower ("CSEF") circuitry is combined with a novel reference bias generator that controls the logic low voltage level by controlling the voltage drop across the current source. The NOR.sub.i circuit utilizes less power than CSEF circuits, has a natural threshold equal to the threshold of CSEF circuits to which it is coupled, has a delay skew of approximately 1:1, and maintains minimum signal levels with respect to variations on V.sub.cc. The reference bias generator compensates for temperature, process variables and variations in the NOR.sub.i circuit and in the power supply.

摘要翻译： 利用以反向有功模式操作的晶体管作为其电流源并具有与电流开关射极跟随器（“CSEF”）电路的逻辑电平兼容的逻辑电平的由半电流开关射极跟随器（“HCSEF”）电路执行的NOR逻辑与 一种新颖的参考偏置发生器，通过控制电流源上的电压降来控制逻辑低电压电平。 NORi电路使用比CSEF电路更少的功率，具有等于其耦合到的CSEF电路的阈值的自然阈值，具有约1：1的延迟偏差，并且相对于Vcc上的变化保持最小信号电平。 参考偏置发生器补偿NORi电路和电源中的温度，过程变量和变化。

公开(公告)号：US5317208A

公开(公告)日：1994-05-31

申请号：US881595

申请日：1992-05-12

申请人： Dennis C. Banker ,  Tore A. Carlson ,  Jack A. Dorler ,  Paul D. Hendricks ,  Walter S. Klara ,  Frank M. Masci ,  James R. Struk

发明人： Dennis C. Banker ,  Tore A. Carlson ,  Jack A. Dorler ,  Paul D. Hendricks ,  Walter S. Klara ,  Frank M. Masci ,  James R. Struk

IPC分类号： G05F3/26 ,  H01L27/082 ,  H03K19/086 ,  H03K19/013

CPC分类号： H01L27/0828 ,  G05F3/265 ,  H03K19/086

摘要： Relatively constant current sources and current mirrors are formed with vertical bipolar transistors operated in the inverse mode. In one embodiment of the invention, an integrated circuit current mirror includes a dual collector vertical NPN bipolar transistor having first and second regions of one conductivity type defining first and second collector regions, respectively, formed within a common third region of opposite conductivity type defining the base of the transistor. The third region is formed within a fourth region defining the emitter of the transistor. The structure of the dual collector vertical transistor is very compact since the two collectors share the same base region which is embedded in a common emitter (inverse collector) pocket. The "inverse" mode vertical transistor can function as a relatively constant current source with a voltage drop (VCEi) across its collector-to-emitter which is substantially less than that of a bipolar transistor operated in a normal mode. Transistors embodying the invention may be used to provide relatively constant current sources to numerous utilization means, such as logic or analog circuits. Due to the low VCEi of the "inverse" mode transistor, the resultant circuits can be operated at a lower operating voltage than prior art circuits. This results in a decrease of power dissipation.

摘要翻译： 相对恒定的电流源和电流镜由以反向模式工作的垂直双极晶体管形成。 在本发明的一个实施例中，集成电路电流镜包括双集电极垂直NPN双极晶体管，其具有分别形成在相反导电类型的公共第三区域内的一种导电类型的第一和第二区域，限定第一和第二集电极区域， 晶体管的基极。 第三区域形成在限定晶体管的发射极的第四区域内。 双集电极垂直晶体管的结构非常紧凑，因为两个集电极共享相同的基极区域，该基极区域嵌入共同的发射极（反向集电极）口袋中。 “逆”模式垂直晶体管可以用作相对恒定的电流源，其电压降（VCEi）跨越其集电极到发射极，其基本上小于在正常模式下工作的双极晶体管的电压降。 体现本发明的晶体管可以用于向诸如逻辑或模拟电路的许多使用装置提供相对恒定的电流源。 由于“反”型晶体管的低VCEi，所得到的电路可以在比现有技术电路低的工作电压下工作。 这导致功耗的降低。

公开(公告)号：US6115731A

公开(公告)日：2000-09-05

申请号：US56722

申请日：1998-04-07

申请人： Paul D. Hendricks

发明人： Paul D. Hendricks

IPC分类号： H03M7/32 ,  G06F7/60 ,  H03M3/02 ,  G06F7/38

CPC分类号： G06F7/602

摘要： A scalable overflow clamp for controlling the level of allowable digital signal overflow in a gain scaler/summer having an initial full-scale range and a feedback path for establishing a feedback gain. The clamp includes a range scaler for determining the feedback gain and generating a modified full-scale range relative to the feedback gain. The modified full-scale range defines a substantially constant overflow capability relative to the feedback gain. An overflow detector senses the overflow conditions and a selector responsive to the overflow detector utilizes the modified full-scale range when overflow conditions are sensed.

摘要翻译： 一种可扩展的溢出钳位器，用于控制具有初始满量程范围的增益缩放器/加法器中的可允许数字信号溢出电平以及用于建立反馈增益的反馈路径。 钳位器包括用于确定反馈增益的范围定标器，并相对于反馈增益产生修正的满量程范围。 改进的满量程范围定义相对于反馈增益的基本恒定的溢出能力。 溢流检测器检测溢出情况，响应于溢流检测器的选择器在检测到溢出条件时利用修改的满量程范围。

公开(公告)号：US06823019B1

公开(公告)日：2004-11-23

申请号：US09363005

申请日：1999-07-30

申请人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith

发明人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith

IPC分类号： H04B1406

CPC分类号： H03H17/04

摘要： DC transients are removed from a digital filter such as a sigma delta filter (in particular from a sigma delta high pass filter) from the outset by presetting an input summing node to a sigma delta modulator. While the input summing node may be preset using any appropriate input, in a disclosed embodiment, a sigma delta high pass filter is preset by switching a partial feedback term between an input containing the non-zero preset value and the normal input comprising the output from the input summing node. The preset value is chosen based on the value of the zero of the transfer function of the sigma delta high pass filter, e.g., with the complement of the gain factor.

摘要翻译： 通过将输入求和节点预设到Σ-Δ调制器，从一开始就从数字滤波器例如Σ-Δ滤波器（特别是从Σ-Δ高通滤波器）中去除DC瞬变。 虽然可以使用任何适当的输入来预设输入求和节点，但是在所公开的实施例中，通过在包含非零预设值的输入和包括输出的正常输入之间切换部分反馈项来预设Σ-Δ高通滤波器 输入求和节点。 基于Σ-Δ高通滤波器的传递函数的零值的值例如以增益因子的补数来选择预设值。

公开(公告)号：US06625278B1

公开(公告)日：2003-09-23

申请号：US09379603

申请日：1999-08-24

申请人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith ,  Steven B. Witmer

发明人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith ,  Steven B. Witmer

IPC分类号： H04M100

CPC分类号： H04M11/062 ,  H04M1/76

摘要： An AC impedance matching architecture which provides programmable AC impedance matching in a given range using a digital filter to filter a signal fed back from the impedance matched line to generate an AC impedance emulation control signal. The AC impedance emulation control signal is combined with a transmit signal (if desired) and drives a voltage controlled current source, which is in parallel with a reference impedance. A voltage is developed across the reference impedance to drive, e.g., the telephone line. The reference impedance is chosen based on a desired maximum AC impedance. The gain of the digital filter, a first order sigma delta filter in the disclosed embodiment, is chosen based on the desired value of the AC impedance. The transfer function of the digital filter is derived based on a desired AC impedance.

摘要翻译： AC阻抗匹配架构，其使用数字滤波器在给定范围内提供可编程AC阻抗匹配，以对从阻抗匹配线反馈的信号进行滤波，以产生AC阻抗仿真控制信号。 交流阻抗仿真控制信号与发射信号（如果需要）组合，并驱动与参考阻抗并联的压控电流源。 在参考阻抗上产生电压以驱动例如电话线。 基于所需的最大AC阻抗来选择参考阻抗。 在所公开的实施例中，数字滤波器，第一级Σ-Δ滤波器的增益是基于AC阻抗的期望值来选择的。 基于所需的AC阻抗导出数字滤波器的传递函数。

公开(公告)号：US06232900B1

公开(公告)日：2001-05-15

申请号：US09299089

申请日：1999-04-26

申请人： Paul D. Hendricks ,  Lane A. Smith

发明人： Paul D. Hendricks ,  Lane A. Smith

IPC分类号： H03M300

CPC分类号： H03H17/0411

摘要： A 2nd order digital filter requiring only one sigma delta modulator is created by implementing (1) a 2nd order feedforward term created by the cascade of two 1st order elements; (2) a 2nd order feedback term created by the cascade of two 1st order elements; and (3) another 2nd order feedback term created by the cascade of two more 1st order elements to eliminate the need for another sigma delta modulator to provide a 2nd order filter. Thus, for the mere ‘cost’ of additional feedback loops, which are small in comparison with the size and complexity of another sigma delta modulator, a second sigma delta modulator is not necessary to implement a 2nd order digital filter in accordance with the principles with the present invention.

摘要翻译： 仅需要一个Σ-Δ调制器的二阶数字滤波器通过实现（1）由两个1阶元件级联产生的二阶前馈项来产生; （2）由两个一阶元素级联产生的二阶反馈项; 和（3）由两个以上的第一级元件的级联产生的另一个二阶反馈项，以消除另一个Σ-Δ调制器提供二阶滤波器的需要。 因此，对于与另一个Σ-Δ调制器的尺寸和复杂度相比较小的附加反馈回路的“成本”，第二个Σ-Δ调制器不需要根据以下原则实现二阶数字滤波器： 本发明。

公开(公告)号：US06674856B1

公开(公告)日：2004-01-06

申请号：US09401995

申请日：1999-09-23

申请人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith ,  Steven B. Witmer

发明人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith ,  Steven B. Witmer

IPC分类号： H04M100

CPC分类号： H04M1/68

摘要： The present invention provides a digital pre-distortion filter in arrangement with a data access arrangement (DAA) on the component side (e.g., in a modem chipset). This arrangement of the pre-distortion filter outside of the DAA allows digital processes such as digital emulation of the central office impedance to remain unaffected by the pre-distortion in the transmitted signal, allowing the dynamic range of the transmitted signal to be flattened to minimize return loss without complicating the transfer function of the digital emulation of the central office complex load. In the case of a digital emulation filter, placement of a digital pre-distortion filter outside of an analog-to-digital (A/D) digital-to-analog (D/A) loop also minimizes the noise otherwise associated with the use of a pre-distortion filter. Thus, benefits of a pre-distortion filter can be gained without interfering with emulation of impedance, and without causing a significant amount of noise in the transmitted signal.

摘要翻译： 本发明提供了一种数字预失真滤波器，其配置为在组件侧（例如，调制解调器芯片组）中的数据访问装置（DAA）。 DAA之前的预失真滤波器的这种布置允许诸如中心局阻抗的数字仿真的数字处理不受传输信号中的预失真的影响，允许传输信号的动态范围被平坦化以最小化 返回损耗，而不会使中心局复杂负载的数字仿真传输功能复杂化。 在数字仿真滤波器的情况下，数字预失真滤波器在模数（A / D）数模（D / A）环路之外的放置也使得与使用相关的噪声最小化 的预失真滤波器。 因此，可以获得预失真滤波器的优点而不干扰阻抗的仿真，并且不会在发射信号中引起大量的噪声。