公开(公告)号：US4821259A

公开(公告)日：1989-04-11

申请号：US904929

申请日：1986-09-05

申请人： Dennis L. DeBruler ,  Edward H. Hafer ,  Thomas L. Hiller ,  James M. Johnson, Jr. ,  Douglas A. Kimber ,  Christopher G. McHarg ,  Scott W. Pector ,  David A. Pierce

发明人： Dennis L. DeBruler ,  Edward H. Hafer ,  Thomas L. Hiller ,  James M. Johnson, Jr. ,  Douglas A. Kimber ,  Christopher G. McHarg ,  Scott W. Pector ,  David A. Pierce

IPC分类号： H04L12/64 ,  H04Q11/04 ,  H04Q11/02

CPC分类号： H04L12/64 ,  H04Q11/0428

摘要： A switching system including a number of switching modules each having a plurality of access ports. Incoming and outgoing packet channels are extended between each switching module and an inter-module packet switch. Each of the switching modules includes both a packet switching unit and a circuit switching unit for switching information to and from the access ports. Each switching module further includes a control unit that controls the switching units and that generates inter-module control packets, and a communication interface that transmits inter-module control packets generated by the control unit on the incoming packet channel to the inter-module packet switch. The communication interface also transmits inter-module control packets received on the outgoing packet channel from the inter-module packet switch to the control unit. The inter-module packet switch concurrently packet switches inter-module control packets received on a number of the incoming packet channels, via mutltiple independent paths to a number of the outgoing packet channels.

摘要翻译： 一种交换系统，包括多个具有多个接入端口的交换模块。 在每个交换模块和模块间分组交换机之间，进出口分组信道被扩展。 每个切换模块包括分组交换单元和用于向接入端口切换信息的电路交换单元。 每个交换模块还包括一个控制单元，其控制交换单元并且产生模块间控制分组;以及通信接口，其将由控制单元在输入分组信道上生成的模块间控制分组发送到模块间分组交换机 。 通信接口还将从输出分组信道接收到的模块间控制分组从模块间分组交换发送到控制单元。 模块间分组交换机并发分组交换在多个输入分组信道上接收的模块间控制分组，经由多个独立路径到多个输出分组信道。

公开(公告)号：US5381405A

公开(公告)日：1995-01-10

申请号：US113481

申请日：1993-08-27

申请人： Thomas H. Daugherty ,  Dennis L. DeBruler ,  Daniel S. Greenberg ,  David J. Hodgdon ,  Douglas J. Murphy

发明人： Thomas H. Daugherty ,  Dennis L. DeBruler ,  Daniel S. Greenberg ,  David J. Hodgdon ,  Douglas J. Murphy

IPC分类号： H04M3/00 ,  H04Q3/58 ,  H04Q11/04 ,  H04M3/42

CPC分类号： H04Q3/58

摘要： A communications switch communicates a message to a particular access network endpoint by forwarding an identification of that endpoint along with the message, link-by-link, through the access network, the forwarding being accomplished by using previously stored routing information identifying, at the switch and at each cross-connection point, a particular downstream link over which the endpoint can ultimately be reached. The links connecting the cross-connection points am time-division-multiplexed links supporting digital loop carrier and fiber-in-the-loop communications. The routing information is generated and stored automatically by having each network element report information about itself upstream into the network.

摘要翻译： 通信交换机通过接入网转发该端点的标识以及该链路的链路，通过使用先前存储的路由信息​​，在该交换机上识别，来完成该消息到特定的接入网络端点 并且在每个交叉连接点处，最终可以到达端点的特定下游链路。 连接交叉连接点的链路是支持数字环路载波和光纤在线通信的时分复用链路。 通过使每个网络单元将关于其自身的信息上报到网络中来自动生成和存储路由信息。

公开(公告)号：US4539637A

公开(公告)日：1985-09-03

申请号：US411899

申请日：1982-08-26

申请人： Dennis L. DeBruler

发明人： Dennis L. DeBruler

IPC分类号： G06F9/46 ,  G06F12/02 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177

CPC分类号： G06F9/544 ,  G06F12/0284 ,  G06F12/0292 ,  G06F15/161 ,  G06F15/173

摘要： A multiprocessor arrangement in which the individual program functions of a program process are executed on different processors. Data shared by different program functions is stored in shared memory and the programs are stored in local memory of the individual processors. One processor calls for the execution of a program function by another processor by causing the program address and a pointer to the program function context to be loaded into a work queue of the called processor. Input/output modules are treated as processors. Facilities are provided for the transfer of blocks of data over the interconnection bus system. Virtual address are translated to physical addresses in one facility common to all processors.

摘要翻译： 在不同处理器上执行程序处理的各个程序功能的多处理器装置。 不同程序功能共享的数据存储在共享存储器中，程序存储在各个处理器的本地存储器中。 一个处理器通过使程序地址和指向程序功能上下文的指针被加载到被调用处理器的工作队列中，要求由另一处理器执行程序功能。 输入/输出模块被视为处理器。 提供了通过互连总线系统传输数据块的设施。 虚拟地址转换为所有处理器通用的一个设备中的物理地址。

公开(公告)号：US5386417A

公开(公告)日：1995-01-31

申请号：US113496

申请日：1993-08-27

申请人： Thomas H. Daugherty ,  Dennis L. DeBruler ,  Daniel S. Greenberg ,  David J. Hodgdon ,  Douglas J. Murphy

发明人： Thomas H. Daugherty ,  Dennis L. DeBruler ,  Daniel S. Greenberg ,  David J. Hodgdon ,  Douglas J. Murphy

IPC分类号： H04Q3/545 ,  H04M3/00 ,  H04Q3/58 ,  H04Q3/66 ,  H04Q11/04 ,  H04M3/42

CPC分类号： H04Q3/58

摘要： A communications switch communicates a message to a particular access network endpoint by forwarding an identification of that endpoint along with the message, link-by-link, through the access network, the forwarding being accomplished by using previously stored routing information identifying, at the switch and at each cross-connection point, a particular downstream link over which the endpoint can ultimately be reached. The links connecting the cross-connection points are multiplexed links supporting digital loop carrier and fiber-in-the-loop communications. The routing information is generated and stored automatically by having each network element report information about itself upstream into the network.

摘要翻译： 通信交换机通过接入网转发该端点的标识以及该链路的链路，通过使用先前存储的路由信息​​，在该交换机上识别，来完成该消息到特定的接入网络端点 并且在每个交叉连接点处，最终可以到达端点的特定下游链路。 连接交叉点的链路是支持数字环路载波和光纤在线通信的复用链路。 通过使每个网络单元将关于其自身的信息上报到网络中来自动生成和存储路由信息。

公开(公告)号：US5231631A

公开(公告)日：1993-07-27

申请号：US853353

申请日：1992-03-16

申请人： Rolfe E. Buhrke ,  Dennis L. DeBruler ,  Vikram Punj

发明人： Rolfe E. Buhrke ,  Dennis L. DeBruler ,  Vikram Punj

IPC分类号： H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5602 ,  H04Q11/0478 ,  H04L2012/5615 ,  H04L2012/5629 ,  H04L2012/563 ,  H04L2012/5632

摘要： The invention relates to methods and apparatus for regulating traffic in a Broadband Integrated Services Digital Network (B-ISDN). Terminal adapters interface between terminals and the B-ISDN. Whenever a first terminal wishes to transmit a data message to a second terminal, the source adapter, connected to the first terminal, allocates transmit bandwidth for the transmission of the message and sends a request message to a destination adapter, connected to the second terminal, for checking availability of and allocating receive bandwidth. The data message is sent only if bandwidth has been allocated on both ends. Overflow traffic is throttled at the adapters before it enters the network, thereby reducing the number of data cells lost because of the limited storage of the network.

摘要翻译： 本发明涉及用于调节宽带综合业务数字网（B-ISDN）业务的方法和装置。 终端适配器在终端和B-ISDN之间接口。 每当第一终端希望向第二终端发送数据消息时，连接到第一终端的源适配器分配用于传输消息的发送带宽，并向与第二终端连接的目的地适配器发送请求消息， 用于检查可用性和分配接收带宽。 只有在两端都分配了带宽的情况下才会发送数据报文。 在适配器进入网络之前，溢出流量被限制在适配器上，从而减少由于网络的有限存储造成的数据单元丢失的数量。

公开(公告)号：US5155858A

公开(公告)日：1992-10-13

申请号：US726143

申请日：1991-06-24

申请人： Dennis L. DeBruler ,  Allen D. Fergeson ,  F. Joseph Glynn ,  Gilbert A. VanDine

发明人： Dennis L. DeBruler ,  Allen D. Fergeson ,  F. Joseph Glynn ,  Gilbert A. VanDine

IPC分类号： G06F9/50 ,  G06F15/173

CPC分类号： G06F15/17337 ,  G06F9/505 ,  G06F9/5083 ,  G06F2209/5021

摘要： A method and apparatus for allocating work requests among a plurality of processors attached to a data ring. Each processor has an interface for communicating with the data ring. The interface for each work request accepting processor has a memory defining a plurality of destination addresses for which the associated processor will accept work requests. Each type of work request has several destination addresses corresponding to different priority levels. If that processor becomes too heavily loaded, it will delete one or more of the destination addresses for which the interface will accept work requests. Such a deletion results in the processor only accepting higher priority requests for a type of work request. Work request generating processors detect work request messages which have not been accepted when they return on the ring. Such messages are then retransmitted at a higher priority, and with a longer delay between consecutive transmissions of the work request message. Advantageously, such an arrangement permits each processor to regulate its own load based on its own measurements of work activity, while permitting repeated attempts to get each work request accepted.

摘要翻译： 一种用于在附接到数据环的多个处理器中分配工作请求的方法和装置。 每个处理器都有一个用于与数据环通信的接口。 每个工作请求接受处理器的接口具有定义多个目的地地址的存储器，相关联的处理器将为其接收工作请求。 每种类型的工作请求具有对应于不同优先级的几个目的地址。 如果处理器负载过重，它将删除接口将接受工作请求的一个或多个目标地址。 这样的删除导致处理器仅接受针对一种工作请求的更高优先级的请求。 工作请求生成处理器检测到工作请求消息在环上返回时未被接受。 然后，这些消息以更高优先级重传，并且在工作请求消息的连续传输之间具有更长的延迟。 有利地，这种布置允许每个处理器基于其自己的工作活动测量来调节其自己的负载，同时允许重复尝试以接收每个工作请求。