公开(公告)号：US08536925B2

公开(公告)日：2013-09-17

申请号：US12598352

申请日：2008-12-29

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Jeffrey J. Nagy ,  Peter J. Nicholas

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Jeffrey J. Nagy ,  Peter J. Nicholas

IPC分类号： H03L5/00

CPC分类号： H03K3/356113 ,  H03K3/0375

摘要： A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).

摘要翻译： 电压转换器电路（320）包括适于接收参考第一电压源（VDD核心）的输入信号的输入级（322），适于连接到第二电压源（VDD33）的锁存器（326） 至少临时存储输入信号的逻辑状态，以及耦合在输入级（322）和锁存器（326）之间的电压钳位（324）。 电压钳（322）用于将锁存器（326）两端的最大电压设定为第一规定电平，并将输入级两端的最大电压设定为第二规定电平。 电压转换器电路（320）在闩锁（326）和电压钳（324）之间的连接处产生第一输出信号（II）。 电压转换器电路在电压钳位器（324）和输入级（322）之间的接点处产生第二输出信号（15）。

公开(公告)号：US08362803B2

公开(公告)日：2013-01-29

申请号：US13031176

申请日：2011-02-18

申请人： Peter J. Nicholas ,  John Christopher Kriz ,  Dipankar Bhattacharya ,  James John Bradley

发明人： Peter J. Nicholas ,  John Christopher Kriz ,  Dipankar Bhattacharya ,  James John Bradley

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K3/356182

摘要： A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

摘要翻译： 电压转换器电路包括适于接收参考第一电压源的输入信号的输入级，适于与第二电压源连接并可操作以至少临时存储输入信号的逻辑状态的第一锁存电路，以及 电压钳耦合在输入级和第一锁存电路之间。 电压钳可用于将输入级两端的最大电压设定到规定的电平。 电压转换器电路在形成在第一锁存电路和电压钳之间的结处的第一输出处产生第一输出信号。 第二锁存电路以反馈配置连接到第一输出端。 第二锁存电路用于将第一输出信号的逻辑状态保持为至少提供给第二锁存电路的第一控制信号的函数，而与第一电压源的状态无关。

公开(公告)号：US20120212256A1

公开(公告)日：2012-08-23

申请号：US13031176

申请日：2011-02-18

申请人： Peter J. Nicholas ,  John Christopher Kriz ,  Dipankar Bhattacharya ,  James John Bradley

发明人： Peter J. Nicholas ,  John Christopher Kriz ,  Dipankar Bhattacharya ,  James John Bradley

IPC分类号： H03K19/0175 ,  H03K5/08

CPC分类号： H03K19/018521 ,  H03K3/356182

摘要： A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

摘要翻译： 电压转换器电路包括适于接收参考第一电压源的输入信号的输入级，适于与第二电压源连接并可操作以至少临时存储输入信号的逻辑状态的第一锁存电路，以及 电压钳耦合在输入级和第一锁存电路之间。 电压钳可用于将输入级两端的最大电压设定到规定的电平。 电压转换器电路在形成在第一锁存电路和电压钳之间的结处的第一输出处产生第一输出信号。 第二锁存电路以反馈配置连接到第一输出端。 第二锁存电路用于将第一输出信号的逻辑状态保持为至少提供给第二锁存电路的第一控制信号的函数，而与第一电压源的状态无关。

公开(公告)号：US08373441B1

公开(公告)日：2013-02-12

申请号：US13236914

申请日：2011-09-20

申请人： John A. Milinichik ,  Peter J. Nicholas ,  Carol A. Huber ,  Antonio M. Marques ,  Daniel J. Delpero

发明人： John A. Milinichik ,  Peter J. Nicholas ,  Carol A. Huber ,  Antonio M. Marques ,  Daniel J. Delpero

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： G06F17/5068

摘要： Described embodiments provide for a semiconductor device comprising a core and one or more input/output (I/O) buffers surrounding the core. The I/O buffers are adapted to transfer signals associated with core circuitry of the core. The I/O buffers comprise I/O cells having a first orientation and I/O cells having a second orientation. Each I/O cell has a corresponding translator having low voltage transistors in a corresponding footprint. The low voltage transistors in the first orientation I/O cells have the first orientation, and the low voltage transistors in the second orientation I/O cells have the first orientation. The footprints of the first orientation I/O cells and the second orientation I/O cells are compatible with one another.

摘要翻译： 所描述的实施例提供了一种半导体器件，其包括芯和围绕芯的一个或多个输入/输出（I / O）缓冲器。 I / O缓冲器适于传输与核心的核心电路相关联的信号。 I / O缓冲器包括具有第一取向的I / O单元和具有第二取向的I / O单元。 每个I / O单元具有相应的占空比中具有低电压晶体管的对应的转换器。 第一定向I / O单元中的低电压晶体管具有第一取向，并且第二取向I / O单元中的低电压晶体管具有第一取向。 第一定向I / O单元和第二定向I / O单元的脚印彼此兼容。