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    MIMcap top plate pull-back
    3.
    发明授权
    MIMcap top plate pull-back 有权
    MIMcap顶板拉回

    公开(公告)号：US06693017B1

    公开(公告)日：2004-02-17

    申请号：US10407587

    申请日：2003-04-04

    申请人： Mohammed Fazil Fayaz ,  Haining Yang ,  Uwe Kerst ,  Joseph J. Mezzapelle

    发明人： Mohammed Fazil Fayaz ,  Haining Yang ,  Uwe Kerst ,  Joseph J. Mezzapelle

    IPC分类号： H01L2120

    CPC分类号： H01L28/40 ,  H01L27/0805

    摘要： A MIM capacitor includes a bottom plate, a capacitor dielectric disposed over the bottom plate, and a top plate disposed over the capacitor dielectric. An etch stop material is disposed over the top plate, and the top plate has a width that is less than the width of the etch stop material width. The top plate edges may be pulled back during the removal of the resist used to pattern the top plate, by the addition of chemistries in the resist etch that are adapted to pull-back or undercut the top plate edges beneath the etch stop material.

    摘要翻译： MIM电容器包括底板，设置在底板上的电容器电介质和设置在电容器电介质上的顶板。 蚀刻停止材料设置在顶板上方，并且顶板的宽度小于蚀刻停止材料宽度的宽度。 在去除用于图案化顶板的抗蚀剂时，顶板边缘可以被拉回，通过在抗蚀剂蚀刻中添加适于在蚀刻停止材料下面的顶板边缘进行拉回或削切的化学物质。

    Etching processes using C4F8 for silicon dioxide and CF4 for titanium nitride
    4.
    发明授权
    Etching processes using C4F8 for silicon dioxide and CF4 for titanium nitride 失效
    使用C4F8作为二氧化硅和CF4用于氮化钛的蚀刻工艺

    公开(公告)号：US07276450B2

    公开(公告)日：2007-10-02

    申请号：US11163836

    申请日：2005-11-01

    申请人： Joseph J. Mezzapelle

    发明人： Joseph J. Mezzapelle

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31116 ,  H01L21/76802

    摘要： Methods of etching a dielectric layer and a cap layer over a conductor to expose the conductor are disclosed. In one embodiment, the methods include the use of a silicon dioxide (SiO2) etching chemistry including octafluorocyclobutane (C4F8) and a titanium nitride (TiN) etching chemistry including tetrafluoro methane (CF4). The methods prevent etch rate degradation and exhibit reduced electro-static discharge (ESD) defects.

    摘要翻译： 公开了在导体上蚀刻介电层和盖层以暴露导体的方法。 在一个实施方案中，所述方法包括使用包括八氟环丁烷（C 4 H 8 F 8）的二氧化硅（SiO 2）蚀刻化学品和 包括四氟甲烷（CF 4 SO 4）的氮化钛（TiN）蚀刻化学。 该方法防止蚀刻速率降低并且显示降低的静电放电（ESD）缺陷。

    Apparatus and method to improve resist line roughness in semiconductor wafer processing
    5.
    发明授权
    Apparatus and method to improve resist line roughness in semiconductor wafer processing 失效

    公开(公告)号：US07018779B2

    公开(公告)日：2006-03-28

    申请号：US10338273

    申请日：2003-01-07

    申请人： Wai-kin Li ,  Rajeev Malik ,  Joseph J. Mezzapelle

    发明人： Wai-kin Li ,  Rajeev Malik ,  Joseph J. Mezzapelle

    IPC分类号： G03F7/00

    CPC分类号： G03F7/091 ,  G03F7/11 ,  Y10S430/151

    摘要： A process for prohibiting amino group transport from the top surface of a layered semiconductor wafer to a photoresist layer introduces a thin film oxynitride over the silicon nitride layer using a high temperature step of nitrous oxide (N2O) plus oxygen (O2) at approximately 300° C. for about 50 to 120 seconds. By oxidizing the silicon nitride layer, the roughness resulting from the adverse affects of amino group transport eliminated. Moreover, this high temperature step, non-plasma process can be used with the more advanced 193 nanometer technology, and is not limited to the 248 nanometer technology. A second method for exposing the silicon nitride layer to an oxidizing ambient, prior to the application of antireflective coating, introduces a mixture of N2H2 and oxygen (O2) ash at a temperature greater than or equal to 250° C. for approximately six minutes. This is followed by an O2 plasma clean and/or an Ozone clean, and then the subsequent layering of the ARC and photoresist.