公开(公告)号：US08497583B2

公开(公告)日：2013-07-30

申请号：US12964448

申请日：2010-12-09

申请人： Dmytro Chumakov ,  Michael Grillberger ,  Heike Berthold ,  Katrin Reiche

发明人： Dmytro Chumakov ,  Michael Grillberger ,  Heike Berthold ,  Katrin Reiche

IPC分类号： H01L29/40

CPC分类号： H01L23/562 ,  H01L2224/16225 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

摘要： A stress compensation region that may be appropriately positioned on a package substrate may compensate for or at least significantly reduce the thermally induced mechanical stress in a sensitive metallization system of a semiconductor die, in particular during the critical reflow process. For example, a stressor ring may be formed so as to laterally surround the chip receiving portion of the package substrate, wherein the stressor ring may efficiently compensate for the thermally induced deformation in the chip receiving portion.

摘要翻译： 可以适当地定位在封装衬底上的应力补偿区域可以补偿或至少显着地降低半导体管芯的敏感金属化系统中的热致机械应力，特别是在临界回流工艺期间。 例如，应力环可以形成为横向围绕封装衬底的芯片接收部分，其中应力环可以有效地补偿芯片接收部分中的热诱导变形。

公开(公告)号：US20110291299A1

公开(公告)日：2011-12-01

申请号：US12964448

申请日：2010-12-09

申请人： Dmytro Chumakov ,  Michael Grillberger ,  Heike Berthold ,  Katrin Reiche

发明人： Dmytro Chumakov ,  Michael Grillberger ,  Heike Berthold ,  Katrin Reiche

IPC分类号： H01L23/58 ,  H01L21/50

CPC分类号： H01L23/562 ,  H01L2224/16225 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

摘要： A stress compensation region that may be appropriately positioned on a package substrate may compensate for or at least significantly reduce the thermally induced mechanical stress in a sensitive metallization system of a semiconductor die, in particular during the critical reflow process. For example, a stressor ring may be formed so as to laterally surround the chip receiving portion of the package substrate, wherein the stressor ring may efficiently compensate for the thermally induced deformation in the chip receiving portion.

摘要翻译： 可以适当地定位在封装衬底上的应力补偿区域可以补偿或至少显着地降低半导体管芯的敏感金属化系统中的热致机械应力，特别是在临界回流工艺期间。 例如，应力环可以形成为横向围绕封装衬底的芯片接收部分，其中应力环可以有效地补偿芯片接收部分中的热诱导变形。

公开(公告)号：US08361844B2

公开(公告)日：2013-01-29

申请号：US12754359

申请日：2010-04-05

申请人： Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Uwe Griebenow

发明人： Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Uwe Griebenow

IPC分类号： H01L21/335

CPC分类号： H01L21/28123 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575

摘要： By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions.

摘要翻译： 通过在高能注入工艺期间在先进的半导体器件的栅电极结构上提供注入阻挡材料，可以实现相对于晶体管的沟道区所需的屏蔽效应。 在稍后的制造阶段中，可以移除注入阻挡部分以将栅极电极的高度降低到期望的水平，以便在层间电介质材料的沉积期间增强工艺条件，从而显着降低产生不规则性的风险，例如 在层间电介质材料中，甚至在密集装填区域也是空隙。

公开(公告)号：US08349744B2

公开(公告)日：2013-01-08

申请号：US12272273

申请日：2008-11-17

申请人： Kai Frohberg ,  Uwe Griebenow ,  Katrin Reiche ,  Heike Berthold

发明人： Kai Frohberg ,  Uwe Griebenow ,  Katrin Reiche ,  Heike Berthold

IPC分类号： H01L21/31

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process.

摘要翻译： 应力松弛注入工艺的增强的效率可以通过沉积厚度较小的第一层并在某些器件区域放松应力松弛注入工艺，从而获得在考虑的晶体管附近获得增加量的基本上松弛的电介质材料，其中期望的 通过进行另外的沉积工艺，可以在其它晶体管之上获得大量的应力介电材料。 因此，通过用中间松弛注入工艺在两个步骤中沉积高应力电介质材料，可以显着地降低高应力电介质材料对特定晶体管（例如密集封装器件区域）的负面影响。

公开(公告)号：US08440534B2

公开(公告)日：2013-05-14

申请号：US13104474

申请日：2011-05-10

申请人： Uwe Griebenow ,  Jan Hoentschel ,  Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Frank Feustel ,  Kerstin Ruttloff

发明人： Uwe Griebenow ,  Jan Hoentschel ,  Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Frank Feustel ,  Kerstin Ruttloff

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/6656 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7836

摘要： Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

公开(公告)号：US20100190309A1

公开(公告)日：2010-07-29

申请号：US12754359

申请日：2010-04-05

申请人： Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Uwe Griebenow

发明人： Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Uwe Griebenow

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575

摘要： By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions.

摘要翻译： 通过在高能注入工艺期间在先进的半导体器件的栅电极结构上提供注入阻挡材料，可以实现相对于晶体管的沟道区所需的屏蔽效应。 在稍后的制造阶段中，可以移除注入阻挡部分以将栅极电极的高度降低到期望的水平，以便在层间电介质材料的沉积期间增强工艺条件，从而显着降低产生不规则性的风险，例如 在层间电介质材料中，甚至在密集装填区域也是空隙。

公开(公告)号：US20090243049A1

公开(公告)日：2009-10-01

申请号：US12272273

申请日：2008-11-17

申请人： Kai Frohberg ,  Uwe Griebenow ,  Katrin Reiche ,  Heike Berthold

发明人： Kai Frohberg ,  Uwe Griebenow ,  Katrin Reiche ,  Heike Berthold

IPC分类号： H01L21/3115 ,  H01L23/58

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process.

摘要翻译： 应力松弛注入工艺的增强的效率可以通过沉积厚度较小的第一层并在某些器件区域放松应力松弛注入工艺，从而获得在考虑的晶体管附近获得增加量的基本上松弛的电介质材料，其中期望的 通过进行另外的沉积工艺，可以在其它晶体管之上获得大量的应力介电材料。 因此，通过用中间松弛注入工艺在两个步骤中沉积高应力电介质材料，可以显着地降低高应力电介质材料对特定晶体管（例如密集封装器件区域）的负面影响。

公开(公告)号：US20090108336A1

公开(公告)日：2009-04-30

申请号：US12115627

申请日：2008-05-06

申请人： Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Uwe Griebenow

发明人： Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Uwe Griebenow

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28123 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575

摘要： By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions.

摘要翻译： 通过在高能注入工艺期间在先进的半导体器件的栅电极结构上提供注入阻挡材料，可以实现相对于晶体管的沟道区所需的屏蔽效应。 在稍后的制造阶段中，可以移除注入阻挡部分以将栅极电极的高度降低到期望的水平，以便在层间电介质材料的沉积期间增强工艺条件，从而显着降低产生不规则性的风险，例如 在层间电介质材料中，甚至在密集装填区域也是空隙。

公开(公告)号：US08470661B2

公开(公告)日：2013-06-25

申请号：US12625222

申请日：2009-11-24

申请人： Kai Frohberg ,  Uwe Griebenow ,  Katrin Reiche ,  Heike Berthold

发明人： Kai Frohberg ,  Uwe Griebenow ,  Katrin Reiche ,  Heike Berthold

IPC分类号： H01L21/8238 ,  H01L21/338

CPC分类号： H01L29/66477 ,  H01L21/28114 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

摘要： During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.

摘要翻译： 在更换栅极方法期间，通过在开口的内侧壁上沉积间隔层并形成对应的间隔元件，可以减少在去除多晶硅材料之后获得的开口的倒锥度。 因此，可以以更高的可靠性沉积含金属的栅电极材料和高k电介质材料。

公开(公告)号：US20110223732A1

公开(公告)日：2011-09-15

申请号：US13104474

申请日：2011-05-10

申请人： Uwe Griebenow ,  Jan Hoentschel ,  Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Frank Feustel ,  Kerstin Ruttloff

发明人： Uwe Griebenow ,  Jan Hoentschel ,  Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Frank Feustel ,  Kerstin Ruttloff

IPC分类号： H01L21/8234

CPC分类号： H01L29/6656 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7836

摘要： Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

摘要翻译： 可以基于不同的米勒电容来调整复合集成电路中相同导电类型的晶体管的不同阈值电压，这可以通过适当地适配间隔物宽度和/或执行倾斜延伸植入来实现。 因此，有效的处理策略可用于可控地调整米勒电容，从而提供低阈值晶体管的增强的晶体管性能，而不是过度复杂的工艺复杂性与常规方法相比，其中阈值电压值可以基于复数晕和 良好的兴奋剂制度。