公开(公告)号：US20220082615A1

公开(公告)日：2022-03-17

申请号：US17468982

申请日：2021-09-08

Applicant: Dolphin Design

Inventor： Sebastien GENEVEY ,  Mathieu LOUVAT ,  Lionel JURE

IPC: G01R31/30 ,  G06F1/3203 ,  G01R31/317 ,  G06F1/08 ,  H03K3/011 ,  H03K5/134

Abstract: The present disclosure relates to an adaptive body biasing or voltage regulation circuit for a circuit region, comprising: a first delay module configured to delay a local clock signal to generate first and second output signals delayed by first and second delays; a multiplexer configured to select one of the first and second output signals; a first slack monitor circuit configured to generate a first detection signal indicating when a slack time of the first and second output signals is less than a first threshold; a voltage generation circuit configured to generate a supply voltage for the circuit region, or at least one biasing voltage for biasing wells of transistors in the circuit region, using a further control loop comprising a process, voltage and/or temperature sensor; and a control circuit configured to adjust a gain of the further control loop based on the first detection signal.

公开(公告)号：US20240322805A1

公开(公告)日：2024-09-26

申请号：US18579159

申请日：2022-07-15

Applicant: DOLPHIN DESIGN

Inventor： Mathieu LOUVAT ,  François JACQUET

IPC: H03K5/08 ,  H03K5/133 ,  H03K19/21

CPC classification number: H03K5/082 ,  H03K5/133 ,  H03K19/21

Abstract: The present disclosure relates to a circuit comprising: —a first timing guard circuit (200) configured to detect when a slack time of a first data signal arriving at a first synchronous device (202) falls below a first threshold (SLG DELAY); and —a second timing guard circuit (200) configured to detect when a slack time of a second data signal arriving at a second synchronous device (202) falls below a second threshold (SLG DELAY), the first and second thresholds being different from each other.