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    CLOCK GENERATOR AND METHOD OF CLOCK GENERATION
    3.
    发明申请
    CLOCK GENERATOR AND METHOD OF CLOCK GENERATION 有权

    公开(公告)号：US20250062751A1

    公开(公告)日：2025-02-20

    申请号：US18802646

    申请日：2024-08-13

    Applicant: DOLPHIN DESIGN

    Inventor： Frédéric POULLET ,  Ayoub BOUNDOUQ

    IPC: H03K3/03 ,  H03K5/133 ,  H03K19/173

    Abstract: The present disclosure relates to a clock generator comprising: a ring oscillator configured to generate an output frequency signal; a frequency detector configured to compare a frequency of the output frequency signal with r times a frequency of a reference frequency signal and to generate a feedback signal; and a control circuit configured to: control a loop delay parameter of the ring oscillator and a supply voltage of the ring oscillator based on the feedback signal; reduce the frequency of the output frequency signal when its frequency is higher than r times the frequency of the reference frequency signal by reducing the supply voltage; and increase the frequency of the output frequency signal when its frequency is lower than r times the frequency of the reference frequency signal by reducing the loop delay parameter.

    ADAPTIVE BODY BIASING OR VOLTAGE REGULATION USING SLACK SENSORS
    5.
    发明申请
    ADAPTIVE BODY BIASING OR VOLTAGE REGULATION USING SLACK SENSORS 有权

    公开(公告)号：US20220082615A1

    公开(公告)日：2022-03-17

    申请号：US17468982

    申请日：2021-09-08

    Applicant: Dolphin Design

    Inventor： Sebastien GENEVEY ,  Mathieu LOUVAT ,  Lionel JURE

    IPC: G01R31/30 ,  G06F1/3203 ,  G01R31/317 ,  G06F1/08 ,  H03K3/011 ,  H03K5/134

    Abstract: The present disclosure relates to an adaptive body biasing or voltage regulation circuit for a circuit region, comprising: a first delay module configured to delay a local clock signal to generate first and second output signals delayed by first and second delays; a multiplexer configured to select one of the first and second output signals; a first slack monitor circuit configured to generate a first detection signal indicating when a slack time of the first and second output signals is less than a first threshold; a voltage generation circuit configured to generate a supply voltage for the circuit region, or at least one biasing voltage for biasing wells of transistors in the circuit region, using a further control loop comprising a process, voltage and/or temperature sensor; and a control circuit configured to adjust a gain of the further control loop based on the first detection signal.

    Adaptive body biasing or voltage regulation using slack sensors
    7.
    发明授权
    Adaptive body biasing or voltage regulation using slack sensors 有权

    公开(公告)号：US12169221B2

    公开(公告)日：2024-12-17

    申请号：US17468982

    申请日：2021-09-08

    Applicant: Dolphin Design

    Inventor： Sebastien Genevey ,  Mathieu Louvat ,  Lionel Jure

    IPC: G06F1/08 ,  G01R31/30 ,  G01R31/317 ,  G06F1/3203 ,  H03K3/011 ,  H03K5/134 ,  H03K5/00

    Abstract: The present disclosure relates to an adaptive body biasing or voltage regulation circuit for a circuit region, comprising: a first delay module configured to delay a local clock signal to generate first and second output signals delayed by first and second delays; a multiplexer configured to select one of the first and second output signals; a first slack monitor circuit configured to generate a first detection signal indicating when a slack time of the first and second output signals is less than a first threshold; a voltage generation circuit configured to generate a supply voltage for the circuit region, or at least one biasing voltage for biasing wells of transistors in the circuit region, using a further control loop comprising a process, voltage and/or temperature sensor; and a control circuit configured to adjust a gain of the further control loop based on the first detection signal.

    Synchronous device with slack guard circuit
    8.
    发明授权
    Synchronous device with slack guard circuit 有权

    公开(公告)号：US11068630B2

    公开(公告)日：2021-07-20

    申请号：US16723069

    申请日：2019-12-20

    Applicant: Dolphin Design

    Inventor： Mathieu Louvat ,  Lionel Jure ,  Vincent Huard

    IPC: G06F30/327 ,  G06F30/3312 ,  H03K19/00 ,  H03K19/017 ,  H03K19/096 ,  G06F119/12 ,  G06F117/04

    Abstract: Embodiments of the present technology provide a synchronous device. The synchronous device provides a first latch configured to store a data input signal during a first state of a first clock signal and a slack guard circuit. The slack guard circuit provides a delay element coupled to the first latch and configured to generate a delayed data signal, a gated-input cell coupled to the delay element and configured to propagate the delayed data signal during the first state of the first clock signal, and a comparator coupled to the first latch and the gated-input cell.

    PULSE COUNTER
    9.
    发明申请
    PULSE COUNTER 有权

    公开(公告)号：US20240426882A1

    公开(公告)日：2024-12-26

    申请号：US18743314

    申请日：2024-06-14

    Applicant: DOLPHIN DESIGN

    Inventor： Konan Constant ESSEY ,  Gaspard TRICAUD

    IPC: G01R23/10 ,  G06F1/12

    Abstract: The present description relates to a pulse counter (200) comprising an asynchronous counter (201) and a circuit (205) configured to trigger a read operation of the value of said asynchronous counter, said circuit (205) being synchronized by a clock signal.

    CIRCUIT FOR DETECTING TIMING VIOLATIONS IN A DIGITAL CIRCUIT
    10.
    发明公开
    CIRCUIT FOR DETECTING TIMING VIOLATIONS IN A DIGITAL CIRCUIT 审中-公开

    公开(公告)号：US20240322805A1

    公开(公告)日：2024-09-26

    申请号：US18579159

    申请日：2022-07-15

    Applicant: DOLPHIN DESIGN

    Inventor： Mathieu LOUVAT ,  François JACQUET

    IPC: H03K5/08 ,  H03K5/133 ,  H03K19/21

    CPC classification number: H03K5/082 ,  H03K5/133 ,  H03K19/21

    Abstract: The present disclosure relates to a circuit comprising: —a first timing guard circuit (200) configured to detect when a slack time of a first data signal arriving at a first synchronous device (202) falls below a first threshold (SLG DELAY); and —a second timing guard circuit (200) configured to detect when a slack time of a second data signal arriving at a second synchronous device (202) falls below a second threshold (SLG DELAY), the first and second thresholds being different from each other.

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