公开(公告)号：US5422837A

公开(公告)日：1995-06-06

申请号：US168114

申请日：1993-12-14

申请人： Donald C. Boothroyd ,  Bruce E. Flocken ,  Minoru Inoshita

发明人： Donald C. Boothroyd ,  Bruce E. Flocken ,  Minoru Inoshita

IPC分类号： G06F11/16 ,  G06F7/02 ,  G06F9/26 ,  G06F9/345 ,  G06F11/10

CPC分类号： G06F11/1641 ,  G06F11/1064

摘要： In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information. Each cache unit includes bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operation, one cache unit employs the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs.

摘要翻译： 为了在包含重复的BPU的CPU中验证完整性的数据操作结果，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作操作，则采用两个高速缓存单元。 每个缓存单元专用于处理半字节的信息，并且包含高度可靠的数据验证逻辑，而不需要从每个BPU提供双字宽输出总线。 通过将每个缓存单元专用于处理半字节的信息来获得降低每个VLSI芯片的引导计数的这个特征。 每个缓存单元包括逐位比较电路，用于在单精度操作的情况下验证从两个BPU接收的半字节结果，并且在双精度操作的情况下，一个高速缓存单元采用相同的逐位比较， 位比较电路，用于两个缓存单元，验证从两个BPU接收到的结果奇偶校验位，并因此验证半字节结果。

公开(公告)号：US5440724A

公开(公告)日：1995-08-08

申请号：US78389

申请日：1993-06-17

申请人： Donald C. Boothroyd ,  Bruce E. Flocken

发明人： Donald C. Boothroyd ,  Bruce E. Flocken

IPC分类号： G01R31/317 ,  G06F11/16 ,  G06F11/25 ,  H04B17/00

CPC分类号： G06F11/1633 ,  G01R31/31701 ,  G06F11/25

摘要： In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information. Each cache unit includes bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operation, one cache unit employs the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs. In a single precision test mode of operation, test signals internal to the BPUs are issued in complementary half-bytes on the normally redundant result busses and are directed to an external logic analyzer or other test equipment for conventional analysis. In addition, when no stores are being made but the BPUs are manipulating data, the test signals may be furnished to the external test equipment in the same manner, the type of operation, single or double precision, being irrelevant.

摘要翻译： 为了在包含重复的BPU的CPU中验证完整性的数据操作结果，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作操作，则采用两个高速缓存单元。 每个缓存单元专用于处理半字节的信息，并且包含高度可靠的数据验证逻辑，而不需要从每个BPU提供双字宽输出总线。 通过将每个缓存单元专用于处理半字节的信息来获得降低每个VLSI芯片的引导计数的这个特征。 每个缓存单元包括逐位比较电路，用于在单精度操作的情况下验证从两个BPU接收的半字节结果，并且在双精度操作的情况下，一个高速缓存单元采用相同的逐位比较， 位比较电路，用于两个缓存单元，验证从两个BPU接收到的结果奇偶校验位，并因此验证半字节结果。 在单精度测试操作模式下，在正常冗余结果总线上以互补的半字节发布BPU内部的测试信号，并将其引导到外部逻辑分析仪或其他测试设备进行常规分析。 另外，当不存在商店但是BPU正在操作数据时，测试信号可以以相同的方式提供给外部测试设备，操作类型或单精度或双精度是无关紧要的。

公开(公告)号：US5263034A

公开(公告)日：1993-11-16

申请号：US594880

申请日：1990-10-09

申请人： Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards ,  Bruce E. Flocken

发明人： Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards ,  Bruce E. Flocken

IPC分类号： G06F11/16

CPC分类号： G06F11/1641

摘要： In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.

摘要翻译： 为了在包括AX（地址和执行）模块，DN（十进制数字）模块和FP（浮点））模块的中央处理器的基本处理单元（BPU）中提供有效的错误检测，每个模块在 主/从对，并且将每个对中执行的数据操作操作的本地结果进行比较，以便在结果被验证以供后续在中央处理器中使用之前进行身份验证。

公开(公告)号：US5408651A

公开(公告)日：1995-04-18

申请号：US127206

申请日：1993-09-27

申请人： Bruce E. Flocken ,  Russell W. Guenthner ,  Clinton B. Eckard ,  Sleiman Chamoun ,  Jeffrey D. Weintraub

发明人： Bruce E. Flocken ,  Russell W. Guenthner ,  Clinton B. Eckard ,  Sleiman Chamoun ,  Jeffrey D. Weintraub

IPC分类号： G06F11/14 ,  G06F11/16

CPC分类号： G06F11/1641 ,  G06F11/1405 ,  G06F11/165

摘要： In order to efficiently recover from a processing error in a central processing trait (CPU) incorporating a cache memory and a basic processing unit, the BPU is provided in duplicate, and all BPU data manipulation operations are performed redundantly. After duplicate data has been obtained from the cache memory and manipulated by the duplicate BPUs, the outputs from the duplicate BPUs are placed on respective master (MRB) and slave (SRB) result busses which are coupled to the cache unit where the results are compared for identity. If the results are not identical, a local error signal is issued. In response to the error signal, the corrupted data is stored into cache, but, before the cache is deliberately frozen, the data is restored again using a segment of the original data withdrawn from the cache memory by the BPUs such that, when the cache is frozen in anticipation of remedial action, the data block whose modification took place during the faulting operation will have been restored to its preprocessing condition. As a result, restart, if possible, can commence at the same point in the process rather than at an earlier point.

摘要翻译： 为了有效地从包含高速缓冲存储器和基本处理单元的中央处理特性（CPU）中的处理错误中恢复，BPU被重复提供，并且所有BPU数据操作操作被冗余地执行。 在从高速缓冲存储器获得并由重复的BPU操作的重复数据之后，来自重复的BPU的输出被放置在相应的主（MRB）和从（SRB）结果总线上，结果总线被连接到比较结果的缓存单元 为身份。 如果结果不相同，则发出本地错误信号。 响应于错误信号，损坏的数据被存储到高速缓存中，但是在高速缓存被有意地冻结之前，使用由高速缓冲存储器从BPU撤出的原始数据的段再次恢复数据，使得当高速缓存 在预期的补救行动中被冻结，在故障操作期间进行修改的数据块将恢复到其预处理条件。 因此，如果可能，重新启动可以在进程的同一点开始，而不是在较早的时候开始。

公开(公告)号：US5195101A

公开(公告)日：1993-03-16

申请号：US546204

申请日：1990-06-28

申请人： Russell W. Guenthner ,  Bruce E. Flocken ,  Ronald E. Lange

发明人： Russell W. Guenthner ,  Bruce E. Flocken ,  Ronald E. Lange

IPC分类号： G06F11/16

CPC分类号： G06F11/1641

摘要： In a Central Processing Unit (CPU) incorporating a Basic Processing Unit (BPU) which includes an address and execution (AX) unit, a decimal numeric (DN) unit and a floating point (FP) unit and also incorporating a cache unit situated logically intermediate the BPU and system memory, BPU data manipulation errors are sensed by duplicating each of the AX, DN and FP chips (i.e., duplicating the BPU) and performing all BPU data manipulation operations redundantly. The outputs from the duplicate BPUs are placed on respective master (MRB) and slave (SRB) result busses which are coupled to the cache unit, and the results are compared, byte-by-byte in the cache unit. If the results are not identical in each byte of the result, the individual chip handling the byte in the cache unit and detecting the no-compare condition issues an individual error signal, and appropriate steps to remedy or otherwise respond to the error signal may be undertaken within the cache unit, within the CPU and within the system.