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18 条记录 (耗时 0.033 秒)

    Traffic management
    4.
    发明申请
    Traffic management 审中-公开
    交通管理

    公开(公告)号：US20050018601A1

    公开(公告)日：2005-01-27

    申请号：US10612552

    申请日：2003-07-01

    申请人： Suresh Kalkunte ,  Hugh Wilkinson ,  Gilbert Wolrich ,  Mark Rosenbluth ,  Donald Hooper

    发明人： Suresh Kalkunte ,  Hugh Wilkinson ,  Gilbert Wolrich ,  Mark Rosenbluth ,  Donald Hooper

    IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L1/00

    CPC分类号： H04L12/5601 ,  H04L2012/561 ,  H04L2012/5636 ,  H04L2012/5679

    摘要： In general, in one aspect, the disclosure describes a system to process packets received over a network. The system includes a receive process of at least one thread of a network processor to receive data of packets belonging to different flows. The system also includes a transmit process of at least one thread to transmit packets received by the receive process. A scheduler process of at least one thread populates at least one schedule of flow service based, at least in part, on quality of service characteristics associated with the different flows. The schedule identifies different flow candidates for service. The system also includes a shaper process of at least one thread to select from the candidate flows for service from the at least one schedule.

    摘要翻译： 一般来说，一方面，本公开描述了一种处理通过网络接收的分组的系统。 该系统包括网络处理器的至少一个线程的接收处理，以接收属于不同流的分组的数据。 系统还包括至少一个线程的发送过程，以发送由接收过程接收的分组。 至少部分地基于与不同流相关联的服务质量特征，至少一个线程的调度器过程填充至少一个流服务调度。 计划确定不同的候选候选人的服务。 该系统还包括至少一个线程的整形过程，以从候选流中选择来自至少一个调度的服务。

    Thread signaling in multi-threaded processor
    5.
    发明授权
    Thread signaling in multi-threaded processor 失效
    线程信令在多线程处理器中

    公开(公告)号：US07111296B2

    公开(公告)日：2006-09-19

    申请号：US10615280

    申请日：2003-07-08

    申请人： Gilbert Wolrich ,  Debra Bernstein ,  Donald Hooper ,  Matthew J. Adiletta ,  William Wheeler

    发明人： Gilbert Wolrich ,  Debra Bernstein ,  Donald Hooper ,  Matthew J. Adiletta ,  William Wheeler

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4843 ,  G06F9/3851

    摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.

    摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。 还描述了用于分组处理的程序线程通信方案。

    Thread signaling in multi-threaded network processor
    6.
    发明授权
    Thread signaling in multi-threaded network processor 失效
    线程信令在多线程网络处理器中

    公开(公告)号：US06625654B1

    公开(公告)日：2003-09-23

    申请号：US09473799

    申请日：1999-12-28

    申请人： Gilbert Wolrich ,  Debra Bernstein ,  Donald Hooper ,  Matthew J. Adiletta ,  William Wheeler

    发明人： Gilbert Wolrich ,  Debra Bernstein ,  Donald Hooper ,  Matthew J. Adiletta ,  William Wheeler

    IPC分类号： G06F1516

    CPC分类号： G06F9/4843 ,  G06F9/3851

    摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.

    摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。 该处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是指向甚至是存储体还是奇数存储器存储器排序存储器引用;以及第二存储器控制器，其基于存储器引用来优化存储器引用 被读取引用或写入引用。 还描述了用于分组处理的程序线程通信方案。

    Circular link list scheduling
    8.
    发明申请
    Circular link list scheduling 有权
    循环链表调度

    公开(公告)号：US20050038793A1

    公开(公告)日：2005-02-17

    申请号：US10641324

    申请日：2003-08-14

    申请人： David Romano ,  Gilbert Wolrich ,  Donald Hooper

    发明人： David Romano ,  Gilbert Wolrich ,  Donald Hooper

    IPC分类号： G06F7/00 ,  H04L12/56

    CPC分类号： H04L49/254 ,  H04L47/50 ,  H04L47/568

    摘要： A scheduling mechanism to control transmission of data units, such as variable size packets or fixed size cells, to ports of a network device such as a switching fabric system. The scheduling mechanism maintains scheduling data structures, including an array storing information for available queues of ports and circular buffers representing nonempty port queues of the available port queues according to classes of service. The scheduling mechanism uses the data structures to make scheduling decisions concerning the scheduling of data units in the nonempty port queues for transmission to the ports.

    摘要翻译： 控制诸如可变大小分组或固定大小小区之类的数据单元的传输到诸如交换结构系统的网络设备的端口的调度机制。 调度机制维护调度数据结构，包括根据服务类别存储可用队列的信息和表示可用端口队列的非空端口队列的循环缓冲区。 调度机制使用数据结构来做出关于非空端口队列中的数据单元的调度的调度决定，以传送到端口。

    Multi-threaded sequenced receive for fast network port stream of packets
    9.
    发明申请
    Multi-threaded sequenced receive for fast network port stream of packets 有权
    多线程排序接收快速网络端口流数据包

    公开(公告)号：US20060156303A1

    公开(公告)日：2006-07-13

    申请号：US11239547

    申请日：2005-09-28

    申请人： Donald Hooper ,  Matthew Adiletta ,  Gilbert Wolrich

    发明人： Donald Hooper ,  Matthew Adiletta ,  Gilbert Wolrich

    IPC分类号： G06F9/46

    CPC分类号： G06F9/546 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/485 ,  G06F9/4881 ,  G06F9/544

    摘要： A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.

    摘要翻译： 一种在网络处理器中处理网络数据的方法包括使用三个或更多个线程来处理数据分组的开始部分，中间部分和结束部分。 第一个线程处理起始部分; 一个或多个中间线程处理中间部分，最后一个线程处理端部。 第一个信息通过第一个缓冲区从第一个线程间接传递到最后一个线程，中间线程逐渐更新第一个信息。 第二个信息通过第二个缓冲区从第一个线程直接传递到最后一个线程。

    Network statistics
    10.
    发明申请
    Network statistics 有权
    网络统计

    公开(公告)号：US20050025055A1

    公开(公告)日：2005-02-03

    申请号：US10628997

    申请日：2003-07-28

    申请人： Sanjeev Jain ,  Donald Hooper

    发明人： Sanjeev Jain ,  Donald Hooper

    IPC分类号： H04L1/00 ,  H04L12/26

    CPC分类号： H04L43/00

    摘要： In general, in one aspect, the disclosure describes a method of tracking a network statistic stored within a collection of bits. The method includes storing the collection of bits storing the network statistic as at least a first portion and a second portion. The first portion includes a set of least-significant bits and the second portion includes a set of more significant bits. The method also includes incrementing the first portion based on a packet and=determining if the incrementing of the first portion caused a designated bit of the first portion to be set. If it is determined that the incrementing of the first portion caused the designated bit to be set, the method increments the value stored by the second portion and resets the designated bit within the first portion.

    摘要翻译： 一般来说，一方面，本公开描述了一种跟踪存储在位集合内的网络统计量的方法。 该方法包括将存储网络统计量的位的集合存储为至少第一部分和第二部分。 第一部分包括一组最低有效位，并且第二部分包括一组更有效位。 该方法还包括基于分组递增第一部分，以及确定第一部分的递增是否导致要设置的第一部分的指定位。 如果确定第一部分的增加导致指定的位被设置，则该方法增加由第二部分存储的值，并且使第一部分内的指定位复位。