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1.发明授权Double shift instruction for micro engine used in multithreaded parallel processor architecture 有权用于多线程并行处理器架构的微型引擎的双移位指令公开(公告)号：US07191309B1
公开(公告)日：2007-03-13
申请号：US10070006
申请日：2000-08-31
CPC分类号： G06F9/30032 , G06F9/32
摘要： A method of operating a processor includes concatenating a first word and a second word to produce an intermediate result, shifting the intermediate result by a specified shift amount and storing the shifted intermediate result in a third word, to create an address.
摘要翻译： 一种操作处理器的方法包括连接第一字和第二字以产生中间结果，将中间结果移位指定的移位量并将移位的中间结果存储在第三个字中，以创建一个地址。
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公开(公告)号：US07111296B2
公开(公告)日：2006-09-19
申请号：US10615280
申请日：2003-07-08
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。 还描述了用于分组处理的程序线程通信方案。
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公开(公告)号：US06625654B1
公开(公告)日：2003-09-23
申请号：US09473799
申请日：1999-12-28
IPC分类号： G06F1516
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。 该处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是指向甚至是存储体还是奇数存储器存储器排序存储器引用;以及第二存储器控制器，其基于存储器引用来优化存储器引用 被读取引用或写入引用。 还描述了用于分组处理的程序线程通信方案。
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公开(公告)号：US20050039182A1
公开(公告)日：2005-02-17
申请号：US10642053
申请日：2003-08-14
申请人： Donald Hooper , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Gilbert Wolrich
发明人： Donald Hooper , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Gilbert Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/5038 , G06F2209/5018 , H04L69/12
摘要： A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.
摘要翻译： 一种用于将数据单元与多线程处理器的线程相关联以用于处理的方法和装置，并且使得每个线程能够在线程执行周期期间对至少两个数据单元执行处理。 线程执行周期在各个阶段之间分割，线程处理的每个数据单元都由不同的相位进行处理。
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公开(公告)号：US20050038964A1
公开(公告)日：2005-02-17
申请号：US10642061
申请日：2003-08-14
申请人： Donald Hooper , Hugh Wilkinson , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Myles Wilde , Gilbert Wolrich
发明人： Donald Hooper , Hugh Wilkinson , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Myles Wilde , Gilbert Wolrich
CPC分类号： G06F12/0842 , G06F12/0804
摘要： A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.
摘要翻译： 使用不同的执行线程和存储器中的公共数据结构来处理与依赖数据流相关联的数据单元的机制。 访问存储器中用于处理的公共数据结构使用单个读取操作和单个写入操作。 以多个多线程处理阶段的方式折叠多个读 - 修改 - 写存储器操作包括控制第一级，其在与第二级相同的数据单元上操作以将上下文状态信息传递到第二级，用于 一致性
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公开(公告)号：USRE41849E1
公开(公告)日：2010-10-19
申请号：US11159427
申请日：2005-06-22
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
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公开(公告)号：US06681300B2
公开(公告)日：2004-01-20
申请号：US09969436
申请日：2001-10-02
IPC分类号： G06F1200
CPC分类号： G06F9/52
摘要： Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to an unlocked memory location and the read lock miss queue contains at least one read lock memory reference request.
摘要翻译： 管理对随机存取存储器的存储器访问包括获取读取锁定存储器引用请求并将读取的锁定存储器引用请求放置在读取锁定未命中队列的结尾，如果读取锁定存储器引用请求访问未锁定的存储器位置并读取 锁定未命中队列至少包含一个读锁定存储器引用请求。
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公开(公告)号：US06587906B2
公开(公告)日：2003-07-01
申请号：US10339221
申请日：2003-01-09
IPC分类号： G06F1300
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
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9.发明授权公开(公告)号：US06532509B1
公开(公告)日：2003-03-11
申请号：US09470541
申请日：1999-12-22
IPC分类号： G06F1314
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
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公开(公告)号：US06324624B1
公开(公告)日：2001-11-27
申请号：US09473798
申请日：1999-12-28
IPC分类号： G06F1318
CPC分类号： G06F9/52
摘要： Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if (1) the read lock memory reference request is requesting access to an unlocked memory location and (2) the read lock miss queue contains at least one read lock memory reference request.
摘要翻译： 管理对随机存取存储器的存储器访问包括获取读锁定存储器引用请求并将读锁定存储器引用请求放置在读锁定未命中队列的末尾，如果（1）读锁定存储器引用请求正在请求访问解锁的存储器位置 和（2）读取锁定未命中队列至少包含一个读取锁定存储器引用请求。
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