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    Implementing Diagnosis of Transitional Scan Chain Defects Using LBIST Test Patterns
    2.
    发明申请
    Implementing Diagnosis of Transitional Scan Chain Defects Using LBIST Test Patterns 有权
    使用LBIST测试模式实施过渡扫描链缺陷诊断

    公开(公告)号：US20100095177A1

    公开(公告)日：2010-04-15

    申请号：US12250085

    申请日：2008-10-13

    申请人： Donato Orazio Forlenza ,  Orazio Pasquale Forlenza ,  Phong T. Tran

    发明人： Donato Orazio Forlenza ,  Orazio Pasquale Forlenza ,  Phong T. Tran

    IPC分类号： G01R31/3185 ,  G06F11/267

    CPC分类号： G01R31/3183 ,  G01R31/318547

    摘要： A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

    摘要翻译： 提供了一种方法，设备和计算机程序产品，用于使用结构逻辑内置自检（LBIST）测试模式实现过渡扫描链缺陷的诊断。 将LBIST测试模式应用于被测设备，并且具有可变环路控制的多个系统时钟序列应用于通过的操作区域，并且扫描数据被卸载。 将LBIST测试模式应用于被测器件，并且将具有可变环路控制的多个系统时钟序列应用于被测器件的故障操作区域，并且扫描数据被卸载。 然后比较从通过的操作区域和故障操作区域卸载数据。 具有不同结果的识别的锁存器被识别为潜在的AC缺陷锁存器。 所识别的潜在AC缺陷锁存器被发送到物理故障分析系统。

    Implementing Isolation of VLSI Scan Chain Using ABIST Test Patterns
    3.
    发明申请
    Implementing Isolation of VLSI Scan Chain Using ABIST Test Patterns 有权
    使用ABIST测试模式实现VLSI扫描链的隔离

    公开(公告)号：US20100095169A1

    公开(公告)日：2010-04-15

    申请号：US12250103

    申请日：2008-10-13

    申请人： Donato Orazio Forlenza ,  Orazio Pasquale Forlenza ,  Phong T. Tran

    发明人： Donato Orazio Forlenza ,  Orazio Pasquale Forlenza ,  Phong T. Tran

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/318536

    摘要： A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

    摘要翻译： 提供了一种方法，装置和计算机程序产品，用于使用结构阵列自检（ABIST）测试模式实现VLSI AC扫描链缺陷的隔离。 ABIST测试图案被应用于被测设备，并且多个ABIST阵列算法被应用在通过的操作区域中并且每个扫描链被卸载。 ABIST测试模式应用于被测设备，并且在被测设备的故障操作区域中应用多个ABIST阵列算法。 然后比较从通过的操作区域和故障操作区域卸载数据。 具有不同结果的识别的锁存器被识别为潜在的AC缺陷锁存器。 所识别的潜在AC缺陷锁存器被发送到物理故障分析系统。

    Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD)
    6.
    发明授权
    Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD) 有权
    阵列内置自检（ABIST）设计/诊断设计（DFT / DFD）的验证

    公开(公告)号：US07921346B2

    公开(公告)日：2011-04-05

    申请号：US12262976

    申请日：2008-10-31

    申请人： Donato Orazio Forlenza ,  Orazio Pasquale Forlenza ,  Bryan J. Robbins ,  Phong T. Tran

    发明人： Donato Orazio Forlenza ,  Orazio Pasquale Forlenza ,  Bryan J. Robbins ,  Phong T. Tran

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318544 ,  G06F11/2236 ,  G11C29/16 ,  G11C29/32 ,  G11C2029/3202

    摘要： A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.

    摘要翻译： 一种用于测试设计可测性/设计诊断（DFT / DFD）和支持自定义微代码数组的BIST功能的方法，系统和计算机程序产品。 在LSSD冲洗和扫描测试完成后，应用ABIST程序来瞄准ABIST阵列的逻辑相关直流（DC）和交流（AC）故障设计可测试性/设计为诊断DFT / DFD功能 支持微代码数组。 通过应用针对ABIST设计为测试故障的生成的LSSD确定性测试模式来确定DFT功能组合逻辑的LSSD测试，以确定支持微代码阵列的DFT是否正常工作。 在阵列周围应用的ABIST DFT电路导致故障时，可能会终止额外的测试。

    VERIFICATION OF ARRAY BUILT-IN SELF-TEST (ABIST) DESIGN-FOR-TEST/DESIGN-FOR-DIAGNOSTICS (DFT/DFD)
    7.
    发明申请
    VERIFICATION OF ARRAY BUILT-IN SELF-TEST (ABIST) DESIGN-FOR-TEST/DESIGN-FOR-DIAGNOSTICS (DFT/DFD) 有权
    校验设计自检（DFT / DFD）设计测试/设计诊断（DFT / DFD）

    公开(公告)号：US20100115337A1

    公开(公告)日：2010-05-06

    申请号：US12262976

    申请日：2008-10-31

    申请人： Donato Orazio Forlenza ,  Orazio Pasquale Forlenza ,  Bryan J. Robbins ,  Phong T. Tran

    发明人： Donato Orazio Forlenza ,  Orazio Pasquale Forlenza ,  Bryan J. Robbins ,  Phong T. Tran

    IPC分类号： G06F11/07

    CPC分类号： G01R31/318544 ,  G06F11/2236 ,  G11C29/16 ,  G11C29/32 ,  G11C2029/3202

    摘要： A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.

    摘要翻译： 一种用于测试设计可测性/设计诊断（DFT / DFD）和支持自定义微代码数组的BIST功能的方法，系统和计算机程序产品。 在LSSD冲洗和扫描测试完成后，应用ABIST程序来瞄准ABIST阵列的逻辑相关直流（DC）和交流（AC）故障设计可测试性/设计为诊断DFT / DFD功能 支持微代码数组。 通过应用针对ABIST设计为测试故障的生成的LSSD确定性测试模式来确定DFT功能组合逻辑的LSSD测试，以确定支持微代码阵列的DFT是否正常工作。 在阵列周围应用的ABIST DFT电路导致故障时，可能会终止额外的测试。

    Diagnosable general purpose test registers scan chain design
    8.
    发明授权
    Diagnosable general purpose test registers scan chain design 有权
    可诊断通用测试寄存器扫描链设计

    公开(公告)号：US07908534B2

    公开(公告)日：2011-03-15

    申请号：US12036320

    申请日：2008-02-25

    申请人： Franco Motika ,  Michael R. Ouellette ,  Phong T. Tran

    发明人： Franco Motika ,  Michael R. Ouellette ,  Phong T. Tran

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318541 ,  G01R31/318536

    摘要： A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L1/L2 master-slave SRL type latch pairs; connects all the system ports of the L1 latches to the Shift Register Input (SRI) and clocked by the system C1-clk while the L1 scan port is clocked by the A-clk and L2 scan port is clocked only by the B-clk. The L1 latches are connected to at least one multiplexer having a first output connected to an input of each odd SRL, and a second output connected to an input port of each even SRL. In another embodiment, the GPTR includes a plurality of multiplexers respectively coupled to the master-slave latch pairs, wherein a first set of multiplexers have their respective output attached to an input of the odd L1 latches, and a second set of the multiplexers have their respective output attached to an input port of the even L1 latches.

    摘要翻译： 用于诊断长不可扫描寄存器链（GPTR）的断层扫描链缺陷的结构设计 - 用于测试和诊断断裂的LSSD扫描链的系统快速将缺陷定位到故障移位寄存器锁存器（SRL） ）对。 GPTR将GPTR扫描链中使用的锁存器修改为标准LSSD L1 / L2主从SL型锁存器对; 将L1锁存器的所有系统端口连接到移位寄存器输入（SRI）并由系统C1-clk计时，而L1扫描端口由A-clk计时，L2扫描端口由B-clk提供时钟。 L1锁存器连接到至少一个多路复用器，其具有连接到每个奇数SRL的输入的第一输出，以及连接到每个偶数SRL的输入端口的第二输出。 在另一个实施例中，GPTR包括分别耦合到主从锁存器对的多个复用器，其中第一组复用器具有附加到奇数L1锁存器的输入的相应输出，并且第二组复用器具有它们 相应的输出附加到偶数L1锁存器的输入端口。

    Automatic transmission shifter with manual shift mode
    10.
    发明授权
    Automatic transmission shifter with manual shift mode 失效
    自动变速箱带手动变速箱

    公开(公告)号：US5791197A

    公开(公告)日：1998-08-11

    申请号：US687167

    申请日：1996-07-24

    申请人： Donald R. Rempinski ,  Phong T. Tran ,  Ronald Bazany ,  Anil Mandala

    发明人： Donald R. Rempinski ,  Phong T. Tran ,  Ronald Bazany ,  Anil Mandala

    IPC分类号： F16H59/02 ,  F16H61/22 ,  F16H61/24 ,  B60K20/02

    CPC分类号： F16H61/22 ,  F16H59/0204 ,  F16H61/24 ,  F16H2059/0239 ,  Y10T74/20067 ,  Y10T74/2014

    摘要： A shifter for an automatic transmission includes a base, a detent member attached to the base, and a shift lever pivotally attached to the base by a ball and socket pivot for multi-axial movement along a configured shift pattern. The shift pattern includes a first shift path segment for shifting the transmission in an automatic mode, a second shift path segment for shifting the transmission in a manual mode, and a transverse path segment for moving between the first and second path segments. In one form the shift pattern is H-shaped, and the shifter includes a pair of switches connected to a vehicle shift control circuit for upshifting and downshifting as the shift lever is selectively moved along the second shift path segment. In the shifter with the H-shaped pattern, an upper and lower leg are pivoted to the base. The lower leg is configured to interconnect with a linkage for operating the automatic transmission, and the upper leg is configured to engage the shift lever when the shift lever is in the first shift path segment but disengage the shift lever when the shift lever is in the second shift path segment. In another form the shift pattern is S-shaped, and the shifter is adapted to, in the manual mode, shift the automatic transmission to specific forward gears (eg first, second, third or overdrive gears) as the shift lever is moved to particular positions along the second shift path segment. The shifter preferably includes a brake-ignition-transmission-shift-interlock system including a bell crank pivoted to the detent member to control movement of the shift lever out of the park position.

    摘要翻译： 用于自动变速器的换档器包括基座，附接到基座的止动构件和通过球窝枢轴枢转地附接到基座的换档杆，用于沿着构造的换档图案进行多轴向运动。 换档模式包括用于以自动模式移动变速器的第一换档路径段，用于在手动模式下移动变速器的第二换档路段，以及用于在第一和第二路径段之间移动的横向路段。 在一种形式中，换档模式是H形的，并且换档器包括连接到车辆换档控制电路的一对开关，用于升档和降档，因为变速杆选择性地沿着第二换档路段移动。 在具有H形图案的换档器中，上腿和下腿枢转到底座。 小腿构造成与用于操作自动变速器的联动装置相互连接，并且大腿构造成当变速杆处于第一换档路径段中时与变速杆接合，但是当变速杆处于 第二换档路段。 在另一种形式中，换档模式是S形的，并且换档器适于在手动模式中，当变速杆移动到特定的位置时，将自动变速器转换到特定的前进档（例如，第一，第二，第三或过驱动齿轮） 沿着第二移位路径段的位置。 变速器优选地包括制动点火变速器 - 换档 - 互锁系统，其包括枢转到止动件的钟形曲柄，以控制换档杆移出停车位置的运动。