公开(公告)号：US20110037521A1

公开(公告)日：2011-02-17

申请号：US12855055

申请日：2010-08-12

申请人： Dong Min KANG ,  Hong Gu JI ,  Hokyun AHN ,  Jong-Won LIM ,  Woojin CHANG ,  Sang-Heung LEE ,  Dong-Young KIM ,  Hae Cheon KIM

发明人： Dong Min KANG ,  Hong Gu JI ,  Hokyun AHN ,  Jong-Won LIM ,  Woojin CHANG ,  Sang-Heung LEE ,  Dong-Young KIM ,  Hae Cheon KIM

IPC分类号： H03F3/04

CPC分类号： H03F3/24 ,  H03F1/565 ,  H03F3/195 ,  H03F2200/222

摘要： Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor.

摘要翻译： 提供了一种功率放大器，包括：耗尽型高电子迁移率晶体管（D模式HEMT），被配置为放大输入到栅极端子的信号，并通过漏极端子输出放大的信号; 输入匹配电路，被配置为使所述栅极端子串联接地; 以及连接在漏极端子和地之间的DC偏置电路。 通过上述配置，HEMT可以仅由单个DC偏置电路偏压而没有任何偏置装置来提供负电压。 此外，可以通过并联电感器和扼流电感器在各种工作频带中提供优异的匹配特性。

公开(公告)号：US20090170250A1

公开(公告)日：2009-07-02

申请号：US12396614

申请日：2009-03-03

申请人： Jae Kyoung MUN ,  Jong Won LIM ,  Woo Jin CHANG ,  Hong Gu JI ,  Ho Kyun AHN ,  Hae Cheon KIM

发明人： Jae Kyoung MUN ,  Jong Won LIM ,  Woo Jin CHANG ,  Hong Gu JI ,  Ho Kyun AHN ,  Hae Cheon KIM

IPC分类号： H01L21/338

CPC分类号： H01L29/66462 ,  H01L29/7785

摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.

摘要翻译： 提供半导体器件的晶体管及其制造方法。 晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层， 所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。 在这种结构中，可以提高晶体管的隔离和开关速度。 此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。 结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

公开(公告)号：US20090146184A1

公开(公告)日：2009-06-11

申请号：US12122982

申请日：2008-05-19

申请人： Jong Won LIM ,  Ho Kyun AHN ,  Hong Gu JI ,  Woo Jin CHANG ,  Jae Kyoung MUN ,  Hae Cheon KIM ,  Hyun Kyu YU

发明人： Jong Won LIM ,  Ho Kyun AHN ,  Hong Gu JI ,  Woo Jin CHANG ,  Jae Kyoung MUN ,  Hae Cheon KIM ,  Hyun Kyu YU

IPC分类号： H01L29/812 ,  H01L21/335

CPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/66462

摘要： Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.

摘要翻译： 提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。 在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部 在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。 因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

公开(公告)号：US20080132194A1

公开(公告)日：2008-06-05

申请号：US11946315

申请日：2007-11-28

申请人： Hong Gu JI ,  Hae Cheon KIM ,  Hyun Kyu YU

发明人： Hong Gu JI ,  Hae Cheon KIM ,  Hyun Kyu YU

IPC分类号： H04B1/26

CPC分类号： H03D7/1425 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1475 ,  H03D2200/0043

摘要： A sub-harmonic mixer is provided, which includes: a mixer core having first and second transistors performing switching operations in response to a local oscillator (LO) signal and a radio frequency (RF) signal; a power source applying bias maximizing nonlinearity of a transistor included in the mixer core; an RF port applying an RF signal to the mixer core; an LO port applying an LO signal to the mixer core; and first and second phase delay circuits in which the RF signals applied to the first and second transistors have a 180-degree phase difference.

摘要翻译： 提供了一种亚谐波混频器，其包括：具有第一和第二晶体管的混频器核，其响应于本地振荡器（LO）信号和射频（RF）信号执行切换操作; 施加偏置最大化混合器核心中包括的晶体管的非线性的电源; 将RF信号施加到混频器核心的RF端口; LO端口将LO信号施加到混频器核心; 以及施加到第一和第二晶体管的RF信号具有180度相位差的第一和第二相位延迟电路。

公开(公告)号：US20080251858A1

公开(公告)日：2008-10-16

申请号：US12122805

申请日：2008-05-19

申请人： Ho Kyun AHN ,  Jong Won LIM ,  Jae Kyoung MUN ,  Hong Gu JI ,  Woo Jin CHANG ,  Hea Cheon KIM

发明人： Ho Kyun AHN ,  Jong Won LIM ,  Jae Kyoung MUN ,  Hong Gu JI ,  Woo Jin CHANG ,  Hea Cheon KIM

IPC分类号： H01L29/49

CPC分类号： H01L29/812 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/778

摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

摘要翻译： 提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。 使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。 由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。 此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。