公开(公告)号：US08722474B2

公开(公告)日：2014-05-13

申请号：US13592589

申请日：2012-08-23

Applicant: Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

Inventor： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L21/338

CPC classification number: H01L29/0649 ,  H01L21/28593 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

Abstract translation: 本发明公开了一种半导体器件，包括阶梯栅电极和制造该半导体器件的方法。 根据本公开的示例性实施例的半导体器件包括：半导体衬底，其具有包括多个外延层的结构，并且包括形成在其最上部的肖特基层的一部分中的下切割区域; 顺序地形成在半导体衬底上的盖层，第一氮化物层和第二氮化物层，以形成台阶栅极绝缘层图案; 以及通过栅极绝缘层图案沉积耐热金属而形成的阶梯形栅电极，其中下切区域包括形成在栅电极和肖特基层之间的空腔。

公开(公告)号：US20130146944A1

公开(公告)日：2013-06-13

申请号：US13592589

申请日：2012-08-23

Applicant: Hyung Sup YOON ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-II Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

Inventor： Hyung Sup YOON ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-II Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L29/812 ,  H01L21/338

CPC classification number: H01L29/0649 ,  H01L21/28593 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

Abstract translation: 本发明公开了一种半导体器件，包括阶梯栅电极和制造该半导体器件的方法。 根据本公开的示例性实施例的半导体器件包括：半导体衬底，其具有包括多个外延层的结构，并且包括形成在其最上部的肖特基层的一部分中的下切割区域; 顺序地形成在半导体衬底上的盖层，第一氮化物层和第二氮化物层，以形成台阶栅极绝缘层图案; 以及通过栅极绝缘层图案沉积耐热金属而形成的阶梯形栅电极，其中下切区域包括形成在栅电极和肖特基层之间的空腔。

公开(公告)号：US20130069173A1

公开(公告)日：2013-03-21

申请号：US13592560

申请日：2012-08-23

Applicant: Woo Jin CHANG ,  Jong Won LIM ,  Ho Kyun AHN ,  Sang Choon KO ,  Sung Bum BAE ,  Chull Won JU ,  Young Rak PARK ,  Jae Kyoung MUN ,  Eun Soo NAM

Inventor： Woo Jin CHANG ,  Jong Won LIM ,  Ho Kyun AHN ,  Sang Choon KO ,  Sung Bum BAE ,  Chull Won JU ,  Young Rak PARK ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66901 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode;and a metal configured to connect the field plate and the source electrode.

Abstract translation: 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。

公开(公告)号：US07973368B2

公开(公告)日：2011-07-05

申请号：US12122982

申请日：2008-05-19

Applicant: Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim ,  Hyun Kyu Yu

Inventor： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/778 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/66462

Abstract: Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.

Abstract translation: 提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。 在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部 在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。 因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

公开(公告)号：US07902572B2

公开(公告)日：2011-03-08

申请号：US12122805

申请日：2008-05-19

Applicant: Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

Inventor： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

IPC: H01L31/072

CPC classification number: H01L29/812 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/778

Abstract: A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

Abstract translation: 提供了具有头部比脚部宽的T形或/或G字形精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。 使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。 由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。 此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

公开(公告)号：US07871874B2

公开(公告)日：2011-01-18

申请号：US12396614

申请日：2009-03-03

Applicant: Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

Inventor： Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

IPC: H01L21/338

CPC classification number: H01L29/66462 ,  H01L29/7785

Abstract: Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.

Abstract translation: 提供半导体器件的晶体管及其制造方法。 晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层， 所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。 在这种结构中，可以提高晶体管的隔离和开关速度。 此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。 结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

公开(公告)号：US07518166B2

公开(公告)日：2009-04-14

申请号：US11179971

申请日：2005-07-12

Applicant: Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

Inventor： Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

IPC: H01L29/74

CPC classification number: H01L29/66462 ,  H01L29/7785

Abstract: Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.

Abstract translation: 提供半导体器件的晶体管及其制造方法。 晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层， 所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。 在这种结构中，可以提高晶体管的隔离和开关速度。 此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。 结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

公开(公告)号：US20080251858A1

公开(公告)日：2008-10-16

申请号：US12122805

申请日：2008-05-19

Applicant: Ho Kyun AHN ,  Jong Won LIM ,  Jae Kyoung MUN ,  Hong Gu JI ,  Woo Jin CHANG ,  Hea Cheon KIM

Inventor： Ho Kyun AHN ,  Jong Won LIM ,  Jae Kyoung MUN ,  Hong Gu JI ,  Woo Jin CHANG ,  Hea Cheon KIM

IPC: H01L29/49

CPC classification number: H01L29/812 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/778

Abstract: A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

Abstract translation: 提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。 使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。 由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。 此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

公开(公告)号：US07419862B2

公开(公告)日：2008-09-02

申请号：US11446750

申请日：2006-06-05

Applicant: Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

Inventor： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/7784 ,  H01L29/1029 ,  H01L29/66462

Abstract: Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.

Abstract translation: 提供了制造假象高电子迁移率晶体管（PHEMT）的方法。 该方法包括以下步骤：制备包括沟道层和作为最上层的覆盖层的衬底; 在封盖层上形成源极和漏极; 在所得结构的整个表面上形成第一保护层，然后图案化第一保护层以暴露沟道区中的覆盖层的一部分; 去除所述覆盖层的暴露部分以形成第一凹陷结构; 在所得结构的整个表面上形成第二保护层，然后构图第二保护层，以暴露第一凹陷结构中的基底的一部分，从而形成第二凹陷结构; 在所得结构的整个表面上形成多层光致抗蚀剂层，然后构图多层光致抗蚀剂层，以通过第二凹陷结构暴露出基板的一部分并形成栅极形开口; 以及沉积金属层以填充所述栅极开口，然后移除所述多层光致抗蚀剂层，以形成通过所述第二凹陷结构连接到所述衬底的栅极。

公开(公告)号：US20070134862A1

公开(公告)日：2007-06-14

申请号：US11446750

申请日：2006-06-05

Applicant: Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

Inventor： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

IPC: H01L21/8234

CPC classification number: H01L29/7784 ,  H01L29/1029 ,  H01L29/66462

Abstract: Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.

Abstract translation: 提供了制造假象高电子迁移率晶体管（PHEMT）的方法。 该方法包括以下步骤：制备包括沟道层和作为最上层的覆盖层的衬底; 在封盖层上形成源极和漏极; 在所得结构的整个表面上形成第一保护层，然后图案化第一保护层以暴露沟道区中的覆盖层的一部分; 去除所述覆盖层的暴露部分以形成第一凹陷结构; 在所得结构的整个表面上形成第二保护层，然后构图第二保护层，以暴露第一凹陷结构中的基底的一部分，从而形成第二凹陷结构; 在所得结构的整个表面上形成多层光致抗蚀剂层，然后构图多层光致抗蚀剂层，以通过第二凹陷结构暴露出基板的一部分并形成栅极形开口; 以及沉积金属层以填充所述栅极开口，然后移除所述多层光致抗蚀剂层，以形成通过所述第二凹陷结构连接到所述衬底的栅极。