公开(公告)号：US20230290858A1

公开(公告)日：2023-09-14

申请号：US18067352

申请日：2022-12-16

申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

发明人： Yukihiro TSUJI

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027

CPC分类号： H01L29/66462 ,  H01L21/0217 ,  H01L21/0271 ,  H01L21/31144 ,  H01L29/401 ,  H01L29/66856

摘要： A method for manufacturing a semiconductor device, includes forming source and drain electrodes on a semiconductor layer provided above a substrate; forming a first insulating film covering a surface of the semiconductor layer, between the source and drain electrodes, forming a second insulating film on the first insulating film, forming a mask on the second insulating film, the mask having an opening between the source and drain electrodes in a plan view viewed in a direction perpendicular to a substrate surface, forming a first gate opening in the first insulating film and forming a second gate opening in the second insulating film, by etching the first and second insulating films through the opening, and forming a gate electrode on the first and second insulating films, the gate electrode making a Schottky contact with the semiconductor layer through the first and second gate openings.

公开(公告)号：US09269793B2

公开(公告)日：2016-02-23

申请号：US14489761

申请日：2014-09-18

申请人： Avogy, Inc.

发明人： Richard J. Brown ,  Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  David P. Bour

IPC分类号： H01L29/20 ,  H01L21/20 ,  H01L21/332 ,  H01L29/66 ,  H01L29/812 ,  H01L29/808 ,  H01L21/02 ,  H01L21/32 ,  H01L29/36 ,  H01L29/47 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/66856 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/32 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/475 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/8122

摘要： A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.

摘要翻译： 半导体结构包括III族氮化物衬底和沿生长方向耦合到III族氮化物衬底的漂移区域。 半导体衬底还包括耦合到漂移区的沟道区。 通道区域由基本沿着生长方向设置的通道侧壁限定。 半导体衬底还包括相对于沟道区域侧向设置的栅极区域。

公开(公告)号：US20150200097A1

公开(公告)日：2015-07-16

申请号：US14558393

申请日：2014-12-02

申请人： Avogy, Inc.

发明人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC分类号： H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L21/2654 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/6631 ,  H01L29/66446 ,  H01L29/66856 ,  H01L29/8083 ,  H01L29/868 ,  H01L29/872

摘要： A method of making an edge terminated semiconductor device includes providing a GaN substrate having a GaN epitaxial layer grown thereon and exposing a portion of the GaN epitaxial layer to ion implantation. The energy dose is selected to provide a resistivity that is at least 90% of maximum achievable resistivity. The method also includes depositing a conductive layer over a portion of the implanted region.

摘要翻译： 制造边缘端接的半导体器件的方法包括提供其上生长有GaN外延层的GaN衬底，并将GaN外延层的一部分暴露于离子注入。 选择能量剂量以提供至少达到最大可实现电阻率的90％的电阻率。 该方法还包括在植入区域的一部分上沉积导电层。

公开(公告)号：US20110068352A1

公开(公告)日：2011-03-24

申请号：US12956784

申请日：2010-11-30

申请人： Makoto Kasu ,  Toshiki Makimoto ,  Kenji Ueda ,  Yoshiharu Yamauchi

发明人： Makoto Kasu ,  Toshiki Makimoto ,  Kenji Ueda ,  Yoshiharu Yamauchi

IPC分类号： H01L29/24

CPC分类号： H01L21/324 ,  C23C16/274 ,  C23C16/278 ,  C30B25/105 ,  C30B29/04 ,  C30B33/02 ,  C30B33/06 ,  H01L21/02013 ,  H01L21/02027 ,  H01L21/02376 ,  H01L21/02433 ,  H01L21/02527 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/0405 ,  H01L21/0415 ,  H01L29/045 ,  H01L29/1602 ,  H01L29/45 ,  H01L29/66037 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/66856 ,  H01L29/732 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/812 ,  H01L33/0054 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide. In this case, the width of the groove and the thickness of the semiconductor board are determined such that light reflected off an interface between the first optical waveguide and the groove is weakened by light reflected from an interface between the groove and the semiconductor board, and by light reflected from an interface between the semiconductor board and the second optical waveguide.

摘要翻译： 集成光波导具有第一光波导，第二光波导和凹槽。 第二光波导耦合到第一光波导并且具有不同于第一光波导的折射率。 凹槽设置成穿过第一光波导的光路并且以第一光波导和第二光波导之间的界面以预定的间隔分开。 确定与界面的间隔和槽的宽度，使得在第一光波导和第二光波导之间的边界处的反射减弱。 半导体板可以设置在第一光波导和第二光波导之间的边界处。 在这种情况下，确定槽的宽度和半导体板的厚度，使得从第一光波导和凹槽之间的界面反射的光被从凹槽和半导体板之间的界面反射的光减弱，以及 通过从半导体板和第二光波导之间的界面反射的光。

公开(公告)号：US07859019B2

公开(公告)日：2010-12-28

申请号：US11674051

申请日：2007-02-12

申请人： Mio Suzuki ,  Akio Iwabuchi

发明人： Mio Suzuki ,  Akio Iwabuchi

IPC分类号： H01L29/778

CPC分类号： H01L29/812 ,  H01L29/2003 ,  H01L29/42324 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/7787

摘要： A HEMT-type field-effect semiconductor device has a main semiconductor region formed on a silicon substrate. The main semiconductor region is a lamination of a buffer layer on the substrate, an electron transit layer on the buffer layer, and an electron supply layer on the electron transit layer. A source and a drain overlie the electron supply layer. A carrier storage layer overlies the electron supply layer via an insulator, and a gate overlies the carrier storage layer via another insulator. Upon application of an initialiser voltage to the gate, the carrier storage layer has stored therein a sufficient amount of carriers to hold the device off even without voltage application to the gate. An initialiser circuit is also disclosed whereby the device is initialized automatically for normally-off operation.

摘要翻译： HEMT型场效应半导体器件具有形成在硅衬底上的主半导体区域。 主半导体区域是衬底上的缓冲层，缓冲层上的电子传输层和电子迁移层上的电子供给层的叠层。 源极和漏极覆盖电子供应层。 载流子存储层经由绝缘体覆盖电子供给层，并且栅极经由另一绝缘体覆盖载流子存储层。 在向栅极施加初始化电压时，载体存储层已经在其中存储了足够量的载流子，以便即使没有电压施加到栅极也可以将器件保持在关闭状态。 还公开了初始化电路，由此该装置被自动初始化以进行常关断操作。

公开(公告)号：US07288152B2

公开(公告)日：2007-10-30

申请号：US10884386

申请日：2004-07-02

申请人： Yasuo Kitaoka ,  Hisashi Minemoto ,  Isao Kidoguchi ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura ,  Masanori Morishita

发明人： Yasuo Kitaoka ,  Hisashi Minemoto ,  Isao Kidoguchi ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura ,  Masanori Morishita

IPC分类号： C30B11/14

CPC分类号： H01L33/32 ,  H01L29/2003 ,  H01L29/66856

摘要： The present invention provides a manufacturing method in which high quality GaN crystals and GaN crystal substrates can be manufactured under mild conditions of low pressure and low temperature. In a method of manufacturing GaN crystals in which in a gas atmosphere containing nitrogen, gallium and the nitrogen are allowed to react with each other to generate GaN crystals in a mixed melt of the gallium and sodium, the gallium and the nitrogen are allowed to react with each other under a pressurizing condition that exceeds atmospheric pressure, and pressure P1 (atm(×1.013×105 Pa)) of the pressurizing condition is set so as to satisfy the condition that is expressed by the following conditional expression (I): P≦P1

摘要翻译： 本发明提供了一种制造方法，其中可以在低压和低温的温和条件下制造高质量的GaN晶体和GaN晶体衬底。 在制造GaN晶体的方法中，其中在含有氮气的气体气氛中，允许镓和氮彼此反应以在镓和钠的混合熔体中产生GaN晶体，使镓和氮反应 在超过大气压的加压条件下彼此相对地设定加压条件的压力P 1（atm（x1.013×10 Pa）），以满足由 （I）：<？in-line-formula description =“In-line formula”end =“lead”？> P <= P 1 <（P + 45），（I） 公式描述=“在线公式”end =“tail”？>其中在表达式（I）中，P（atm（x1.013×10 Pa））表示最小压力， 在混合熔体的温度T℃下产生GaN晶体。

公开(公告)号：US20060276043A1

公开(公告)日：2006-12-07

申请号：US10550040

申请日：2004-03-22

申请人： Mark Johnson ,  Douglas Barlage

发明人： Mark Johnson ,  Douglas Barlage

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  B82Y10/00 ,  H01L21/3088 ,  H01L29/66318 ,  H01L29/66856 ,  H01L29/66924

摘要： Methods and systems for multiperiod, edge definition lithography are disclosed. According to one method, a first material is isotropically deposited on a substrate and on a field mesa also located on the substrate. The first masking material is then anisotropically removed from the substrate to leave a nanometer-pitched sidewall adjacent to the field mesa. A second masking material is then isotropically deposited on the substrate, the sidewall, and the field mesa. The second masking material is then anisotropically removed from the substrate to leave a second nanometer-pitched sidewall adjacent to the first sidewall. The process may be repeated to create alternating nanometer-pitched sidewalls of the first and second masking materials. One of the first and second masking materials may then be etched from the substrate to leave nanometer-pitched channels in one of the masking materials. The channels may be used to etch nanometer-pitched features in the substrate.

摘要翻译： 公开了用于多周期，边缘清晰度光刻的方法和系统。 根据一种方法，第一材料被各向同性地沉积在基底上以及也位于基底上的场台面上。 然后将第一掩模材料从基底各向异性地移除，以留下与场台面相邻的纳米级的侧壁。 然后将第二掩蔽材料各向同性地沉积在基底，侧壁和场台面上。 然后将第二掩模材料从基板各向异性地移除以留下与第一侧壁相邻的第二纳米级的侧壁。 可以重复该过程以产生第一和第二掩蔽材料的交替的纳米级侧壁。 然后可以从衬底蚀刻第一和第二掩模材料中的一个，以在掩模材料之一中留下纳米间距的通道。 通道可以用于蚀刻衬底中的纳米级的特征。

公开(公告)号：US07067361B2

公开(公告)日：2006-06-27

申请号：US10706641

申请日：2003-11-12

申请人： Scott T. Allen ,  John W. Palmour ,  Terrence S. Alcorn

发明人： Scott T. Allen ,  John W. Palmour ,  Terrence S. Alcorn

IPC分类号： H01L21/338

CPC分类号： H01L29/8128 ,  H01L21/7605 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66856 ,  H01L29/812

摘要： SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs. Also, source and drain ohmic contacts may be formed directly on the n-type channel layer, thus, the n+ regions need not be fabricated and the steps associated with such fabrication may be eliminated from the fabrication process. Methods of fabricating such SiC MESFETs and gate structures for SiC FETs as well as passivation layers are also disclosed.

摘要翻译： 公开了利用基本上不含深层掺杂剂的半绝缘SiC衬底的SiC MESFET。 半绝缘衬底的利用可能会降低MESFET的反向栅极效应。 还提供了具有两个凹陷栅极结构的SiC MESFET。 还提供了具有选择性掺杂的p型缓冲层的MESFET。 使用这种缓冲层可以将输出电导降低3倍，并且与传统的p型缓冲层相比，产生比SiC MESFET增加3db的功率增益。 还可以向p型缓冲层提供接地触点，并且p型缓冲层可以由两层p型层制成，其中在衬底上形成的层具有较高的掺杂剂浓度。 根据本发明实施例的SiC MESFET也可以使用铬作为肖特基栅极材料。 此外，可以利用氧化物 - 氮化物 - 氧化物（ONO）钝化层来降低SiC MESFET中的表面效应。 此外，源极和漏极欧姆接触可以直接形成在n型沟道层上，因此，不需要制造n +区域，并且可以从制造过程中消除与这种制造相关的步骤 。 还公开了制造这种SiC MESFET和用于SiC FET以及钝化层的栅极结构的方法。

公开(公告)号：US20060022218A1

公开(公告)日：2006-02-02

申请号：US11189842

申请日：2005-07-27

申请人： Yasuyuki Masumoto ,  Atsushi Watanabe ,  Kenichi Hidaka ,  Eiji Yasuda

发明人： Yasuyuki Masumoto ,  Atsushi Watanabe ,  Kenichi Hidaka ,  Eiji Yasuda

IPC分类号： H01L31/0328

CPC分类号： H01L29/812 ,  H01L29/045 ,  H01L29/66856

摘要： The present invention, which aims to provide a gallium arsenide field-effect transistor that can reduce degradation of field-effect transistor characteristics, and to realize miniaturization of the transistor, includes: a substrate; a mesa which includes a channel layer and is formed on the substrate; a source electrode formed on the mesa; a drain electrode; and a gate electrode, wherein, on the mesa, a top pattern is formed in which finger portions of the source electrode and the drain electrode which are formed in comb-shape are located so as to interdigitate, and a gate electrode is formed between the source electrode and the drain electrode, while common portions, which are base parts of the finger portions of the source and drain electrodes, are formed on the surface of the mesa, and the part located below the straight portion which is parallel to the finger portions of the gate electrode is electrically separated from the part located below a corner portion that connects neighboring straight portions of the gate electrode.

摘要翻译： 本发明旨在提供一种能够降低场效应晶体管特性劣化并实现晶体管的小型化的砷化镓场效应晶体管，包括：基板; 包括沟道层并形成在所述衬底上的台面; 形成在台面上的源电极; 漏电极; 以及栅电极，其中，在所述台面上形成顶部图案，其中所述源电极和所述漏电极的形成为梳形的指部分被定位成叉指，并且在所述栅电极之间形成栅电极 源电极和漏电极，而作为源电极和漏电极的指部的基部的公共部分形成在台面的表面上，并且位于平行于指状部分的直线部分下方的部分 的电极与位于连接栅电极的相邻直线部分的角部下方的部分电分离。

公开(公告)号：US20050048686A1

公开(公告)日：2005-03-03

申请号：US10884386

申请日：2004-07-02

申请人： Yasuo Kitaoka ,  Hisashi Minemoto ,  Isao Kidoguchi ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura ,  Masanori Morishita

发明人： Yasuo Kitaoka ,  Hisashi Minemoto ,  Isao Kidoguchi ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura ,  Masanori Morishita

IPC分类号： H01L21/338 ,  H01L29/20 ,  H01L33/32 ,  H01L21/00 ,  C30B1/00 ,  H01L21/36

CPC分类号： H01L33/32 ,  H01L29/2003 ,  H01L29/66856

摘要： The present invention provides a manufacturing method in which high quality GaN crystals and GaN crystal substrates can be manufactured under mild conditions of low pressure and low temperature. In a method of manufacturing GaN crystals in which in a gas atmosphere containing nitrogen, gallium and the nitrogen are allowed to react with each other to generate GaN crystals in a mixed melt of the gallium and sodium, the gallium and the nitrogen are allowed to react with each other under a pressurizing condition that exceeds atmospheric pressure, and pressure P1 (atm (×1.013×105 Pa)) of the pressurizing condition is set so as to satisfy the condition that is expressed by the following conditional expression (I): P≦P1

摘要翻译： 本发明提供了一种制造方法，其中可以在低压和低温的温和条件下制造高质量的GaN晶体和GaN晶体衬底。 在制造GaN晶体的方法中，其中在含有氮气的气体气氛中，允许镓和氮彼此反应以在镓和钠的混合熔体中产生GaN晶体，使镓和氮反应 在超过大气压的加压条件下彼此相关，并且将加压条件的压力P1（atm（x1.013×10 5 Pa））设定为满足由以下条件式（I）表示的条件， ：P <= P1 <（P + 45）（I），其中在表达式（I）中，P（atm（x1.013×10 Pa））表示在温度下产生GaN晶体所需的最小压力 T°C。 的混合熔体。