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    Field effect transistor and method for manufacturing the same
    4.
    发明授权
    Field effect transistor and method for manufacturing the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US07387955B2

    公开(公告)日：2008-06-17

    申请号：US11454721

    申请日：2006-06-16

    Applicant: Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

    Inventor： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

    IPC: H01L21/44

    CPC classification number: H01L29/812 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/778

    Abstract: A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

    Abstract translation: 提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。 使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。 由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。 此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

    Method of manufacturing field effect transistor
    5.
    发明授权
    Method of manufacturing field effect transistor 有权
    制造场效应晶体管的方法

    公开(公告)号：US07183149B2

    公开(公告)日：2007-02-27

    申请号：US11180726

    申请日：2005-07-14

    Applicant: Ho Kyun Ahn ,  Jong Won Lim ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim

    Inventor： Ho Kyun Ahn ,  Jong Won Lim ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim

    IPC: H01L21/338

    CPC classification number: H01L29/66856 ,  H01L29/66462

    Abstract: Provided is a method of manufacturing a field effect transistor (FET). The method includes steps of: forming an ohmic metal layer on a substrate in source and drain regions; sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein a lowermost resist pattern is exposed in the first region, and the insulating layer is exposed in the second region; exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns. In this method, transistors having different threshold voltages can be manufactured without additional mask patterns using the least number of processes, with the results that the cost of production can be reduced and the stability and productivity of semiconductor devices can be improved.

    Abstract translation: 提供了制造场效应晶体管（FET）的方法。 该方法包括以下步骤：在源极和漏极区域的衬底上形成欧姆金属层; 在所得结构的整个表面上顺序地形成绝缘层和多层抗蚀剂层，并且同时形成除了欧姆金属层以外的第一区域和不包括欧姆金属层的第二区域中具有不同形状的抗蚀剂图案，其中最下面 抗蚀剂图案在第一区域中暴露，并且绝缘层在第二区域中暴露; 通过分别使用抗蚀剂图案作为蚀刻掩模，同时蚀刻暴露的绝缘层和暴露的最下面的抗蚀剂图案来暴露衬底和绝缘层; 对曝光的衬底进行凹陷处理并蚀刻暴露的绝缘层以露出衬底; 以及在衬底上形成具有彼此不同蚀刻深度的栅极凹陷区域，沉积预定的栅极金属和去除抗蚀剂图案。 在该方法中，可以使用最少数量的工艺来制造具有不同阈值电压的晶体管，而不需要额外的掩模图案，结果可以降低生产成本，并且可以提高半导体器件的稳定性和生产率。

    Carrier cup of planet carrier
    7.
    发明授权
    Carrier cup of planet carrier 有权
    载体杯行星架

    公开(公告)号：US08062167B2

    公开(公告)日：2011-11-22

    申请号：US12179213

    申请日：2008-07-24

    Applicant: Wang Kweon Lee ,  Hyun Ku Lee ,  Sang Bum Baek ,  Ki Jung Han ,  Seock Chan Kang ,  Jae Hyuk Choi ,  Kisoo Huh ,  Hyu Tae Shim ,  Woo Jin Chang

    Inventor： Wang Kweon Lee ,  Hyun Ku Lee ,  Sang Bum Baek ,  Ki Jung Han ,  Seock Chan Kang ,  Jae Hyuk Choi ,  Kisoo Huh ,  Hyu Tae Shim ,  Woo Jin Chang

    IPC: F16H57/08

    CPC classification number: F16H57/082

    Abstract: The present invention relates to a carrier cup of a planet carrier that improves strength thereof and reduces noise occurring in an automatic transmission by changing an interior circumferential shape of a leg. The carrier cup of a planet carrier according to an exemplary embodiment of the present invention at which pinion gears are mounted such that the pinion gears are rotatably supported thereby may include a carrier plate provided with a carrier hole for mounting a carrier shaft and a plurality of pinion holes for mounting the pinion gears, and a plurality of legs extending perpendicularly from one side surface of the carrier plate, wherein radial thickness of the leg is changed along a circumferential direction thereof.

    Abstract translation: 本发明涉及一种行星架的承载杯，其通过改变腿的内部圆周形状来改善其强度并减少在自动变速器中发生的噪音。 根据本发明的示例性实施例的行星架的行星架，其中安装小齿轮使得小齿轮由其可旋转地支撑，其可以包括：承载板，其设置有用于安装行星架轴的承载孔和多个 用于安装小齿轮的小齿轮孔和从承载板的一个侧表面垂直延伸的多个腿，其中腿的径向厚度沿其圆周方向改变。

    AFFINITY SEPARATION BY PARTITION ENHANCING MATERIAL CONJUGATED BIOMOLECULES IN AQUEOUS TWO-PHASE EXTRACTION SYSTEM
    8.
    发明申请
    AFFINITY SEPARATION BY PARTITION ENHANCING MATERIAL CONJUGATED BIOMOLECULES IN AQUEOUS TWO-PHASE EXTRACTION SYSTEM 有权
    在两相萃取系统中分层增强材料结合生物分子的亲和力分离

    公开(公告)号：US20090209735A1

    公开(公告)日：2009-08-20

    申请号：US12303364

    申请日：2008-01-21

    Applicant: Yoon-Mo Koo ,  Woo-Jin Chang ,  Hye-Mee Park

    Inventor： Yoon-Mo Koo ,  Woo-Jin Chang ,  Hye-Mee Park

    IPC: C07K1/14 ,  C07H1/00 ,  C12N5/06 ,  C12N9/96

    CPC classification number: C07K1/22

    Abstract: The present invention relates to a method for separating a material that has affinity to an antibody by using a protein-antibody conjugate with modified partition characteristics, more precisely a method for affinity separation to separate a material specifically binds to an antibody, in which an antibody is conjugated to a protein to modify partition characteristics of the protein-antibody conjugate. The method of the present invention can be effectively and widely used as a safe and efficient separation method for biomolecules since it takes advantages of safe aqueous two-phase extraction system and high selective molecular specific conjugation.

    Abstract translation: 本发明涉及通过使用具有改良的分隔特征的蛋白质 - 抗体缀合物分离对抗体具有亲和力的材料的方法，更准确地说，分离材料以分离材料特异性结合抗体的方法，其中抗体 与蛋白质缀合以改变蛋白质 - 抗体缀合物的分配特征。 本发明的方法可以有效和广泛地用作生物分子的安全有效的分离方法，因为它具有安全的水相两相萃取系统和高选择性分子特异性共轭的优点。

    Method of forming T- or gamma-shaped electrode
    9.
    发明申请
    Method of forming T- or gamma-shaped electrode 审中-公开
    形成T形或γ形电极的方法

    公开(公告)号：US20080124852A1

    公开(公告)日：2008-05-29

    申请号：US11605508

    申请日：2006-11-28

    Applicant: Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Woo Jin Chang ,  Hong Gu Ji ,  Hae Cheon Kim

    Inventor： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Woo Jin Chang ,  Hong Gu Ji ,  Hae Cheon Kim

    IPC: H01L21/338

    CPC classification number: H01L29/4232 ,  H01L21/28587 ,  H01L21/28593

    Abstract: A method of forming a fine T- or gamma-shaped gate electrode is provided, which is performed by a lithography process using a multi-layered photoresist layer having various sensitivities, deposition of an insulating layer, and an etching process. The method includes: a first step of depositing a first insulating layer on a semiconductor substrate; a second step of coating at least two photoresist layers with different sensitivities from each other on the first insulating layer, and patterning the photoresist layers to have openings which are different in size; a third step of etching the first insulating layer using the photoresist layers as etch masks to form a step hole in which a part contacting the substrate is narrower than an upper part thereof, and removing the photoresist layers; a fourth step of forming a photoresist layer on the first insulating layer, and forming an opening in the photoresist layer to have a T- or gamma-shaped gate head pattern; a fifth step of performing a gate recess process with respect to the gate pattern; and a sixth step of depositing a gate metal on the gate pattern, and removing the photoresist layers.

    Abstract translation: 提供了一种通过使用具有各种灵敏度的多层光致抗蚀剂层，沉积绝缘层和蚀刻工艺的光刻工艺来形成精细的T形或γ形栅电极的方法。 该方法包括：在半导体衬底上沉积第一绝缘层的第一步骤; 在所述第一绝缘层上涂覆彼此具有不同灵敏度的至少两个光致抗蚀剂层的第二步骤，以及使所述光致抗蚀剂层图案化以具有尺寸不同的开口; 使用光致抗蚀剂层作为蚀刻掩模来蚀刻第一绝缘层以形成步骤孔的第三步骤，其中与衬底接触的部分比其上部更窄，并且去除光致抗蚀剂层; 在所述第一绝缘层上形成光致抗蚀剂层，以及在所述光致抗蚀剂层中形成具有T形或γ形门头图案的开口的第四步骤; 执行相对于栅极图案的栅极凹槽工艺的第五步骤; 以及在栅极图案上沉积栅极金属和去除光致抗蚀剂层的第六步骤。

    POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    10.
    发明申请
    POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 失效
    功率半导体器件及其制造方法

    公开(公告)号：US20130069173A1

    公开(公告)日：2013-03-21

    申请号：US13592560

    申请日：2012-08-23

    Applicant: Woo Jin CHANG ,  Jong Won LIM ,  Ho Kyun AHN ,  Sang Choon KO ,  Sung Bum BAE ,  Chull Won JU ,  Young Rak PARK ,  Jae Kyoung MUN ,  Eun Soo NAM

    Inventor： Woo Jin CHANG ,  Jong Won LIM ,  Ho Kyun AHN ,  Sang Choon KO ,  Sung Bum BAE ,  Chull Won JU ,  Young Rak PARK ,  Jae Kyoung MUN ,  Eun Soo NAM

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66901 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

    Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode;and a metal configured to connect the field plate and the source electrode.

    Abstract translation: 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。

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