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    Power factor correction circuit for correcting power factor
    3.
    发明授权
    Power factor correction circuit for correcting power factor 有权
    用于校正功率因数的功率因数校正电路

    公开(公告)号：US08791677B2

    公开(公告)日：2014-07-29

    申请号：US13162793

    申请日：2011-06-17

    申请人： Jeong Mo Yang ,  Chang Sik Yoo ,  Yung Jin Moon ,  Yong Seong Roh ,  Joong Ho Choi ,  Jae Shin Lee ,  Jung Chul Gong ,  Yu Jin Jang

    发明人： Jeong Mo Yang ,  Chang Sik Yoo ,  Yung Jin Moon ,  Yong Seong Roh ,  Joong Ho Choi ,  Jae Shin Lee ,  Jung Chul Gong ,  Yu Jin Jang

    IPC分类号： H02M3/156

    CPC分类号： H02M1/4225 ,  Y02B70/126 ,  Y02P80/112

    摘要： There is provided a power factor correction circuit capable of correcting a power factor of a power converting module through increasing an input current by switching a main switching element of a power converting module on the basis of a first reference wave having a slope based on a first signal and an error voltage, in particular, by limiting a switching frequency on the basis of a first reference wave having a slope based on a second signal lower than a first signal and an error voltage when the switching frequency of the main switching element increases because an input voltage of the power converting module is low.

    摘要翻译： 提供了一种功率因数校正电路，其能够通过增加输入电流来校正功率转换模块的功率因数，所述功率因数校正电路通过基于第一参考波来切换功率转换模块的主开关元件，所述第一基准波具有基于第一 信号和误差电压，特别是通过基于具有基于低于第一信号的第二信号的斜率的第一参考波和当主开关元件的开关频率增加时的误差电压来限制开关频率，因为 电力转换模块的输入电压低。

    Data alignment circuit and method of semiconductor memory apparatus
    4.
    发明授权
    Data alignment circuit and method of semiconductor memory apparatus 有权
    半导体存储装置的数据对准电路及方法

    公开(公告)号：US08072822B2

    公开(公告)日：2011-12-06

    申请号：US12649066

    申请日：2009-12-29

    申请人： Chun Seok Jeong ,  Kee Teok Park ,  Chang Sik Yoo ,  Jang Woo Lee ,  Hong Jung Kim

    发明人： Chun Seok Jeong ,  Kee Teok Park ,  Chang Sik Yoo ,  Jang Woo Lee ,  Hong Jung Kim

    IPC分类号： G11C7/22

    CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222

    摘要： A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes.

    摘要翻译： 半导体存储装置的数据对准电路包括：数据选通时钟相位控制块，被配置为响应于选通延迟码来控制数据选通时钟信号的相位，并产生延迟的选通时钟信号; 多个数据相位控制块，被配置为响应于数据延迟码来控制输入数据的相位并产生延迟的数据; 多个数据对准块被配置为响应延迟的选通时钟信号来锁存延迟的数据，并产生锁存的数据和对准的数据; 以及延迟码生成块，被配置为执行确定所述锁存数据的相位的操作，并生成所述选通延迟码和所述数据延迟码。

    Data equalizing circuit and data equalizing method
    5.
    发明授权
    Data equalizing circuit and data equalizing method 有权
    数据均衡电路和数据均衡方法

    公开(公告)号：US08817866B2

    公开(公告)日：2014-08-26

    申请号：US13407478

    申请日：2012-02-28

    申请人： Chun Seok Jeong ,  Jae Jin Lee ,  Chang Sik Yoo ,  Jang Woo Lee ,  Seok Joon Kang

    发明人： Chun Seok Jeong ,  Jae Jin Lee ,  Chang Sik Yoo ,  Jang Woo Lee ,  Seok Joon Kang

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03878 ,  H04L25/03012

    摘要： A data equalizing circuit includes an equalizer configured to output data according to a control code; and a detection unit configured to divide the data into N number of calculation periods, count data transition frequencies for the N calculation periods, calculate dispersion values of the data transition frequencies for the N calculation periods, and output the control code corresponding to a largest dispersion value, in response to a counting interruption signal and a counting completion signal, wherein n is equal to or greater than 2, N is greater than n, and the data is divided to n number of unit intervals (UI), andwherein a phase shift of each of the calculation periods with respect to its corresponding UI is different from a phase shift of any of the other calculation periods with respect to its corresponding UI.

    摘要翻译： 数据均衡电路包括：均衡器，被配置为根据控制码输出数据; 以及检测单元，被配置为将数据划分为N个计算周期，用于N个计算周期的计数数据转换频率，计算N个计算周期的数据转换频率的色散值，并输出与最大色散对应的控制码 响应于计数中断信号和计数完成信号，其中n等于或大于2，N大于n，并且数据被划分为n个单位间隔（UI），并且其中相位 每个计算周期相对于其对应的UI的移位不同于任何其他计算周期相对于其对应的UI的相移。

    Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data
    6.
    发明授权
    Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data 有权
    具有预取数据排序的存储器件分配在预取数据路径逻辑，电路和预取数据排序方法中

    公开(公告)号：US06549444B2

    公开(公告)日：2003-04-15

    申请号：US09834493

    申请日：2001-04-12

    申请人： Kye-Hyun Kyung ,  Chang Sik Yoo

    发明人： Kye-Hyun Kyung ,  Chang Sik Yoo

    IPC分类号： G11C506

    CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C2207/107

    摘要： A memory device is adapted for prefetching data. The memory device has a memory cell array, with local sense amplifiers for receiving data bits prefetched from the memory cell array. The memory device also includes a serializer, and data paths that connect the local sense amplifiers to the serializer. Crossover connections are interposed between stages of the data paths. These transfer data bits between the data paths. Preferably they do that as part of being gates between the stages, which are in turn controlled by a clock. This way ordering is distributed within the data paths, and thus does not limit how fast the clock may become. In addition, the space used remains at a fundamental minimum.

    摘要翻译： 存储器件适于预取数据。 存储器件具有存储单元阵列，其具有用于接收从存储器单元阵列预取的数据位的局部读出放大器。 存储器件还包括串行器，以及将本地读出放大器连接到串行器的数据路径。 交叉连接插在数据路径的各个阶段之间。 这些数据路径之间传输数据位。 优选地，它们作为在阶段之间的门的一部分，其又由时钟控制。 这样排序分布在数据路径内，因此不会限制时钟可能变得多快。 此外，使用的空间仍然是最基本的。

    Data equalizing circuit and data equalizing method
    7.
    发明授权
    Data equalizing circuit and data equalizing method 有权
    数据均衡电路和数据均衡方法

    公开(公告)号：US08520725B2

    公开(公告)日：2013-08-27

    申请号：US13407546

    申请日：2012-02-28

    申请人： Chun Seok Jeong ,  Jae Jin Lee ,  Chang Sik Yoo ,  Jang Woo Lee ,  Seok Joon Kang

    发明人： Chun Seok Jeong ,  Jae Jin Lee ,  Chang Sik Yoo ,  Jang Woo Lee ,  Seok Joon Kang

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03038

    摘要： A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

    摘要翻译： 数据均衡电路包括均衡器，其被配置为根据控制码的值控制数据的增益并输出控制器增益; 以及检测单元，被配置为将数据的n个周期分成N个周期，在改变控制码的值的同时，计算n / N个周期的数据转换频率，计算数据的1 / N个周期的数据转换频率的色散值， n / N周期的数据转换频率，最后输出对应于最大色散值的控制码的值，其中n等于或大于2，并且被设置为使得各个n / N周期的边界 数据在1 UI数据中具有不同的位置。