公开(公告)号：US07312130B2

公开(公告)日：2007-12-25

申请号：US10977385

申请日：2004-10-29

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-Il Cho

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-Il Cho

IPC分类号： H01L21/20

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

摘要： Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

摘要翻译： 形成电容器结构的方法可以包括在衬底上形成绝缘层，在绝缘层上形成第一电容器电极，在第一电容器电极的部分上形成电容器电介质层，以及在电容器电介质层上形成第二电容器电极， 电容器介电层位于第一和第二电容器电极之间。 更具体地，第一电容器电极可以在其中限定空腔，其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。 还讨论了相关结构。

公开(公告)号：US20060040443A1

公开(公告)日：2006-02-23

申请号：US11154152

申请日：2005-06-16

申请人： Sung-Il Cho ,  Jong-Kyu Kim ,  Byeong-Yun Nam ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee

发明人： Sung-Il Cho ,  Jong-Kyu Kim ,  Byeong-Yun Nam ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee

IPC分类号： H01L21/8244

CPC分类号： H01L28/60 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507

摘要： A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.

摘要翻译： 形成电容器的方法可以包括在包括氟和氧的环境中蚀刻金属氮化物层以形成电容器电极。

公开(公告)号：US07329574B2

公开(公告)日：2008-02-12

申请号：US11154152

申请日：2005-06-16

申请人： Sung-Il Cho ,  Jong-Kyu Kim ,  Byeong-Yun Nam ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee

发明人： Sung-Il Cho ,  Jong-Kyu Kim ,  Byeong-Yun Nam ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507

摘要： A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.

摘要翻译： 形成电容器的方法可以包括在包括氟和氧的环境中蚀刻金属氮化物层以形成电容器电极。

公开(公告)号：US07291531B2

公开(公告)日：2007-11-06

申请号：US11048995

申请日：2005-02-02

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

摘要翻译： 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层 电极在下电极上。

公开(公告)号：US20080087931A1

公开(公告)日：2008-04-17

申请号：US11869400

申请日：2007-10-09

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L27/108 ,  H01L21/3205 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

摘要翻译： 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层， 选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

公开(公告)号：US07736970B2

公开(公告)日：2010-06-15

申请号：US11869400

申请日：2007-10-09

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

摘要翻译： 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层， 选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

公开(公告)号：US20050130371A1

公开(公告)日：2005-06-16

申请号：US11048995

申请日：2005-02-02

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3213

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

公开(公告)号：US08941165B2

公开(公告)日：2015-01-27

申请号：US12779300

申请日：2010-05-13

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/314 ,  H01L21/316

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

摘要翻译： 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层 电极在下电极上。

公开(公告)号：US08461687B2

公开(公告)日：2013-06-11

申请号：US13072907

申请日：2011-03-28

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L29/40 ,  H01L29/66

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

摘要翻译： 具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位 设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管 和周边晶体管上电极。 位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

公开(公告)号：US20110241102A1

公开(公告)日：2011-10-06

申请号：US13072907

申请日：2011-03-28

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L29/78

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

摘要翻译： 具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位 设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管 和周边晶体管上电极。 位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。