公开(公告)号：US20160027787A1

公开(公告)日：2016-01-28

申请号：US14847324

申请日：2015-09-08

申请人： Je-Min Park ,  Seok-Hyun Lim ,  Tae-Yong Song ,  Hyun-Chul Yoon ,  Yoo-Sang Hwang ,  Hyeon-Ok Jung

发明人： Je-Min Park ,  Seok-Hyun Lim ,  Tae-Yong Song ,  Hyun-Chul Yoon ,  Yoo-Sang Hwang ,  Hyeon-Ok Jung

IPC分类号： H01L27/108 ,  H01L21/3213

CPC分类号： H01L27/10855 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1085 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

摘要： An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.

摘要翻译： 电子器件可以包括衬底和衬底上的多个间隔开的衬垫。 每个垫可以包括第一，第二，第三和第四侧，第一和第三侧可以是基本上直的相对侧，并且第二和第四侧可以是相对的弯曲的侧面。 还讨论了相关方法，设备和结构。

公开(公告)号：US08461687B2

公开(公告)日：2013-06-11

申请号：US13072907

申请日：2011-03-28

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L29/40 ,  H01L29/66

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

摘要翻译： 具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位 设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管 和周边晶体管上电极。 位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

公开(公告)号：US20110241102A1

公开(公告)日：2011-10-06

申请号：US13072907

申请日：2011-03-28

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L29/78

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

摘要翻译： 具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位 设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管 和周边晶体管上电极。 位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

公开(公告)号：US07510914B2

公开(公告)日：2009-03-31

申请号：US11447944

申请日：2006-06-07

申请人： Hyun-Chul Yoon ,  Jong-Kyu Kim ,  Jang-Bin Yim ,  Sang-Dong Kwon ,  Sung-Gil Choi

发明人： Hyun-Chul Yoon ,  Jong-Kyu Kim ,  Jang-Bin Yim ,  Sang-Dong Kwon ,  Sung-Gil Choi

IPC分类号： H01L21/82

CPC分类号： H01L27/101 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.

摘要翻译： 提供具有多个保险丝的半导体器件及其形成方法。 该半导体器件具有包括具有单元区域和/或保险丝盒区域的衬底的熔丝。 可以在基板上形成第一绝缘中间层。 可以在第一绝缘中间层上形成第一蚀刻停止层。 可以在单元区域的第一蚀刻停止层上形成包括阻挡层，金属层和/或覆盖层的金属布线。 彼此间隔开的保险丝可以形成在保险丝盒区域的第一蚀刻停止层上。 每个熔断器可以包括阻挡层和/或金属层。 具有暴露熔丝盒区域的开口的第二绝缘夹层可以形成在金属布线和/或第一蚀刻停止层上。 蚀刻停止层可以允许保险丝更均匀地形成并且降低断开保险丝的可能性。

公开(公告)号：US08901645B2

公开(公告)日：2014-12-02

申请号：US13864347

申请日：2013-04-17

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/108

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

摘要翻译： 具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位 设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管 和周边晶体管上电极。 位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

公开(公告)号：US20130228856A1

公开(公告)日：2013-09-05

申请号：US13864347

申请日：2013-04-17

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L29/78

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

公开(公告)号：US20130015062A1

公开(公告)日：2013-01-17

申请号：US13542398

申请日：2012-07-05

申请人： Yun Hee Ku ,  Yong Ju Yang ,  Yoo Min Park ,  Seung Yeon Song ,  Yong Duk Han ,  Moo Sub Kim ,  Hyun Chul Yoon

发明人： Yun Hee Ku ,  Yong Ju Yang ,  Yoo Min Park ,  Seung Yeon Song ,  Yong Duk Han ,  Moo Sub Kim ,  Hyun Chul Yoon

IPC分类号： G01N27/327 ,  H01R43/16

CPC分类号： C12Q1/003 ,  G01N33/723 ,  Y10T29/49204

摘要： Disclosed herein are an electrode for measuring glycoprotein and a preparation method thereof. In the electrode, cystamine is bound to the electrode surface, and boronic acid is conjugated to the cystamine. Thus, an increased amount of boronic acid can be bound to the electrode surface, so that the amount of glycoprotein can be more accurately measured using the electrode.

摘要翻译： 本文公开了一种糖蛋白测定用电极及其制备方法。 在电极中，胱胺与电极表面结合，硼酸与胱氨酸结合。 因此，硼酸的量可以与电极表面结合，从而可以使用电极更精确地测量糖蛋白的量。

公开(公告)号：US20100304501A1

公开(公告)日：2010-12-02

申请号：US12740348

申请日：2007-11-09

申请人： Dae Sik Lee ,  Rae Man Park ,  Sung Lyul Maeng ,  Moon Youn Jung ,  Seon Hee Park ,  Hyun Chul Yoon

发明人： Dae Sik Lee ,  Rae Man Park ,  Sung Lyul Maeng ,  Moon Youn Jung ,  Seon Hee Park ,  Hyun Chul Yoon

IPC分类号： G01N33/543 ,  G01N30/96

CPC分类号： G01N33/54366 ,  B01L3/502707 ,  B01L3/50273 ,  B01L2200/0673 ,  B01L2300/0636 ,  B01L2300/0645 ,  B01L2300/0816 ,  B01L2300/089 ,  B01L2300/161 ,  B01L2400/0436 ,  B01L2400/0496 ,  G01N33/5438

摘要： Disclosed is a bio lab-on-a-chip. The bio lab-on-a-chip is provided on a piezoelectric thin film on a substrate, and includes a sensing unit to sense a bio signal and a fluidic control unit which controls a transfer of a microfluid adjacent to the sensing unit. Provided is also a method of fabricating the bio lab-on-a-chip. The method includes the steps of forming a piezoelectric thin film, forming a sensing unit to sense a bio signal of a microfluid on the piezoelectric thin film, and forming a fluidic control unit located adjacent to the sensing unit.

摘要翻译： 公开了一种生物实验室芯片。 片上生物实验室设置在基板上的压电薄膜上，并且包括用于感测生物信号的感测单元和控制与感测单元相邻的微流体传输的流体控制单元。 还提供了一种制造生物芯片实验室的方法。 该方法包括形成压电薄膜的步骤，形成感测单元以感测压电薄膜上的微流体的生物信号，以及形成位于感测单元附近的流体控制单元。

公开(公告)号：US09461051B2

公开(公告)日：2016-10-04

申请号：US14847324

申请日：2015-09-08

申请人： Je-Min Park ,  Seok-Hyun Lim ,  Tae-Yong Song ,  Hyun-Chul Yoon ,  Yoo-Sang Hwang ,  Hyeon-Ok Jung

发明人： Je-Min Park ,  Seok-Hyun Lim ,  Tae-Yong Song ,  Hyun-Chul Yoon ,  Yoo-Sang Hwang ,  Hyeon-Ok Jung

IPC分类号： H01L27/108 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L27/10855 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1085 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

摘要： An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.

摘要翻译： 电子器件可以包括衬底和衬底上的多个间隔开的衬垫。 每个垫可以包括第一，第二，第三和第四侧，第一和第三侧可以是基本上直的相对侧，并且第二和第四侧可以是相对的弯曲的侧面。 还讨论了相关方法，设备和结构。

公开(公告)号：US09231104B2

公开(公告)日：2016-01-05

申请号：US14527450

申请日：2014-10-29

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L27/00 ,  H01L29/00 ,  H01L29/78 ,  H01L29/423 ,  H01L27/105 ,  H01L29/45 ,  H01L27/108

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

摘要翻译： 具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位 设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管 和周边晶体管上电极。 位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。