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    Phase change memory device and method of fabricating the same
    1.
    发明授权
    Phase change memory device and method of fabricating the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US07767568B2

    公开(公告)日：2010-08-03

    申请号：US11905244

    申请日：2007-09-28

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Jong-Chan Shin ,  Dong-Ho Ahn ,  Jun-Soo Bae ,  Jeong-Hee Park

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Jong-Chan Shin ,  Dong-Ho Ahn ,  Jun-Soo Bae ,  Jeong-Hee Park

    IPC分类号： H01L21/3205

    CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

    摘要： A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane.

    摘要翻译： 提供了一种相变存储器件及其制造方法。 具有第一表面的第一电极设置在基板上。 具有与第一表面不同的第二表面的第二电极在基板上。 第二电极可以与第一电极间隔开。 可以对应于第一电极形成第三电极。 可以对应于第二电极形成第四电极。 可以在第一表面和第三电极之间插入第一相变图案。 可以在第二表面和第四电极之间插入第二相变图案。 第一和第二相变图案的上表面可以在同一平面上。

    Phase change memory devices including memory cells having different phase change materials and related methods and systems
    5.
    发明申请
    Phase change memory devices including memory cells having different phase change materials and related methods and systems 有权
    相变存储器件包括具有不同相变材料的存储单元以及相关的方法和系统

    公开(公告)号：US20080068879A1

    公开(公告)日：2008-03-20

    申请号：US11881062

    申请日：2007-07-25

    申请人： Dong-Ho Ahn ,  Hideki Horii ,  Jun-Soo Bae

    发明人： Dong-Ho Ahn ,  Hideki Horii ,  Jun-Soo Bae

    IPC分类号： G11C11/00 ,  H01L45/00

    CPC分类号： G11C11/5678 ,  G11C7/04 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

    摘要： A phase change memory device may include an integrated circuit substrate and first and second phase change memory elements on the integrated circuit substrate. The first phase change memory element may include a first phase change material having a first crystallization temperature. The second phase change memory element may include a second phase change material having a second crystallization temperature. Moreover, the first and second crystallization temperatures may be different so that the first and second phase change memory elements are programmable at different temperatures. Related methods and systems are also discussed.

    摘要翻译： 相变存储器件可以包括集成电路衬底以及集成电路衬底上的第一和第二相变存储元件。 第一相变存储元件可以包括具有第一结晶温度的第一相变材料。 第二相变存储元件可以包括具有第二结晶温度的第二相变材料。 此外，第一和第二结晶温度可以不同，使得第一和第二相变存储元件可在不同温度下编程。 还讨论了相关方法和系统。

    Phase change memory devices including memory cells having different phase change materials and related methods and systems
    6.
    发明授权
    Phase change memory devices including memory cells having different phase change materials and related methods and systems 有权
    相变存储器件包括具有不同相变材料的存储单元以及相关的方法和系统

    公开(公告)号：US07558100B2

    公开(公告)日：2009-07-07

    申请号：US11881062

    申请日：2007-07-25

    申请人： Dong-Ho Ahn ,  Hideki Horii ,  Jun-Soo Bae

    发明人： Dong-Ho Ahn ,  Hideki Horii ,  Jun-Soo Bae

    IPC分类号： G11C11/00

    CPC分类号： G11C11/5678 ,  G11C7/04 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

    摘要： A phase change memory device may include an integrated circuit substrate and first and second phase change memory elements on the integrated circuit substrate. The first phase change memory element may include a first phase change material having a first crystallization temperature. The second phase change memory element may include a second phase change material having a second crystallization temperature. Moreover, the first and second crystallization temperatures may be different so that the first and second phase change memory elements are programmable at different temperatures. Related methods and systems are also discussed.

    摘要翻译： 相变存储器件可以包括集成电路衬底以及集成电路衬底上的第一和第二相变存储元件。 第一相变存储元件可以包括具有第一结晶温度的第一相变材料。 第二相变存储元件可以包括具有第二结晶温度的第二相变材料。 此外，第一和第二结晶温度可以不同，使得第一和第二相变存储元件可在不同温度下编程。 还讨论了相关方法和系统。

    Phase changeable memory cell array region and method of forming the same
    9.
    发明申请
    Phase changeable memory cell array region and method of forming the same 有权
    相变存储单元阵列区域及其形成方法

    公开(公告)号：US20070111440A1

    公开(公告)日：2007-05-17

    申请号：US11581012

    申请日：2006-10-16

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L29/94

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

    Phase changeable memory cell array region and method of forming the same
    10.
    发明授权
    Phase changeable memory cell array region and method of forming the same 有权
    相变存储单元阵列区域及其形成方法

    公开(公告)号：US08039298B2

    公开(公告)日：2011-10-18

    申请号：US12617782

    申请日：2009-11-13

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L21/06 ,  H01L21/00 ,  G11C11/00

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。