公开(公告)号：US20050110012A1

公开(公告)日：2005-05-26

申请号：US10997441

申请日：2004-11-23

申请人： Dong-Hun Lee ,  Jong-Hyon Ahn ,  Do-Yul Yoo ,  Sung-Gun Kang

发明人： Dong-Hun Lee ,  Jong-Hyon Ahn ,  Do-Yul Yoo ,  Sung-Gun Kang

IPC分类号： H01L21/027 ,  G03F7/20 ,  H01L23/544 ,  H01L29/10

CPC分类号： G03F7/70633 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  H01L2924/00

摘要： An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.

摘要翻译： 覆盖标记包括形成在半导体衬底上的至少一个孔阵列和与孔阵列相邻的至少一个线性沟槽。 孔阵列可以沿着预定方向形成为与线性沟槽相邻。 当检测到在半导体衬底的预定部分形成的图形之间的对准误差时，重叠标记可以提供具有所需宽度和高电平的光的对比度，从而可以精确地检测和校正形成在半导体衬底上的图案的对准误差 使用重叠标记。

公开(公告)号：US06285540B1

公开(公告)日：2001-09-04

申请号：US09560359

申请日：2000-04-28

申请人： Dong-Hun Lee ,  Jong-Hyon Ahn

发明人： Dong-Hun Lee ,  Jong-Hyon Ahn

IPC分类号： H02H504

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  Y10S148/055 ,  H01L2924/00

摘要： The present invention provides a fuse of a semiconductor device and a method of forming a fuse of a semiconductor device. The method of the invention includes forming an underlying metal conductor on a semiconductor substrate, forming an insulating film over the underlying metal conductor, and selectively etching regions of the insulating film. One of the regions of the insulating film is etched to form a via contact region exposing the underlying metal conductor. A second region is etched to form a groove in the insulating film for the fuse metal. Metal is buried within the second etched region of the insulating film and the via contact region to respectively form a fuse metal pattern and a via contact metal layer.

摘要翻译： 本发明提供一种半导体器件的熔丝和形成半导体器件的熔丝的方法。 本发明的方法包括在半导体衬底上形成下面的金属导体，在下面的金属导体上形成绝缘膜，并选择性地蚀刻绝缘膜的区域。 蚀刻绝缘膜的一个区域以形成暴露下面的金属导体的通孔接触区域。 蚀刻第二区域以在用于熔丝金属的绝缘膜中形成凹槽。 金属被埋在绝缘膜和通孔接触区域的第二蚀刻区域内，以分别形成熔丝金属图案和通孔接触金属层。

公开(公告)号：US06300233B1

公开(公告)日：2001-10-09

申请号：US09714392

申请日：2000-11-16

申请人： Dong-Hun Lee ,  Jong-Hyon Ahn

发明人： Dong-Hun Lee ,  Jong-Hyon Ahn

IPC分类号： H01L2144

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a fuse of a semiconductor device and a method of forming a fuse of a semiconductor device. The method of the invention includes forming an underlying metal conductor on a semiconductor substrate, forming an insulating film over the underlying metal conductor, and selectively etching regions of the insulating film. One of the regions of the insulating film is etched to form a via contact region exposing the underlying metal conductor. A second region is etched to form a groove in the insulating film for the fuse metal. Metal is buried within the second etched region of the insulating film and the via contact region to respectively form a fuse metal pattern and a via contact metal layer. The fuse metal pattern can be formed from copper and/or tungsten.

摘要翻译： 本发明提供一种半导体器件的熔丝和形成半导体器件的熔丝的方法。 本发明的方法包括在半导体衬底上形成下面的金属导体，在下面的金属导体上形成绝缘膜，并选择性地蚀刻绝缘膜的区域。 蚀刻绝缘膜的一个区域以形成暴露下面的金属导体的通孔接触区域。 蚀刻第二区域以在用于熔丝金属的绝缘膜中形成凹槽。 金属被埋在绝缘膜和通孔接触区域的第二蚀刻区域内，以分别形成熔丝金属图案和通孔接触金属层。 熔丝金属图案可以由铜和/或钨形成。

公开(公告)号：US07288848B2

公开(公告)日：2007-10-30

申请号：US10997441

申请日：2004-11-23

申请人： Dong-Hun Lee ,  Jong-Hyon Ahn ,  Do-Yul Yoo ,  Sung-Gun Kang

发明人： Dong-Hun Lee ,  Jong-Hyon Ahn ,  Do-Yul Yoo ,  Sung-Gun Kang

IPC分类号： H01L23/544

CPC分类号： G03F7/70633 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  H01L2924/00

摘要： An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.

摘要翻译： 覆盖标记包括形成在半导体衬底上的至少一个孔阵列和与孔阵列相邻的至少一个线性沟槽。 孔阵列可以沿着预定方向形成为与线性沟槽相邻。 当检测到在半导体衬底的预定部分形成的图形之间的对准误差时，重叠标记可以提供具有所需宽度和高电平的光的对比度，从而可以精确地检测和校正形成在半导体衬底上的图案的对准误差 使用重叠标记。

公开(公告)号：US06175145B1

公开(公告)日：2001-01-16

申请号：US09163826

申请日：1998-09-30

申请人： Dong-Hun Lee ,  Jong-Hyon Ahn

发明人： Dong-Hun Lee ,  Jong-Hyon Ahn

IPC分类号： H01L2900

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a fuse of a semiconductor device and a method of forming a fuse of a semiconductor device. The method of the invention includes forming an underlying metal conductor on a semiconductor substrate, forming an insulating film over the underlying metal conductor, and selectively etching regions of the insulating film. One of the regions of the insulating film is etched to form a via contact region exposing the underlying metal conductor. A second region is etched to form a groove in the insulating film for the fuse metal. Metal is buried within the second etched region of the insulating film and the via contact region to respectively form a fuse metal pattern and a via contact metal layer. The fuse metal pattern can be formed from copper and/or tungsten.

摘要翻译： 本发明提供一种半导体器件的熔丝和形成半导体器件的熔丝的方法。 本发明的方法包括在半导体衬底上形成下面的金属导体，在下面的金属导体上形成绝缘膜，并选择性地蚀刻绝缘膜的区域。 蚀刻绝缘膜的一个区域以形成暴露下面的金属导体的通孔接触区域。 蚀刻第二区域以在用于熔丝金属的绝缘膜中形成凹槽。 金属被埋在绝缘膜和通孔接触区域的第二蚀刻区域内，以分别形成熔丝金属图案和通孔接触金属层。 熔丝金属图案可以由铜和/或钨形成。

公开(公告)号：US6074940A

公开(公告)日：2000-06-13

申请号：US122501

申请日：1998-07-24

申请人： Dong-Hun Lee ,  Jong-Hyon Ahn

发明人： Dong-Hun Lee ,  Jong-Hyon Ahn

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L21/44

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  Y10S148/055

摘要： The present invention provides a fuse of a semiconductor device and a method of forming a fuse of a semiconductor device. The method of the invention includes forming an underlying metal conductor on a semiconductor substrate, forming an insulating film over the underlying metal conductor, and selectively etching regions of the insulating film. One of the regions of the insulating film is etched to form a via contact region exposing the underlying metal conductor. A second region is etched to form a groove in the insulating film for the fuse metal. Metal is buried within the second etched region of the insulating film and the via contact region to respectively form a fuse metal pattern and a via contact metal layer.

摘要翻译： 本发明提供一种半导体器件的熔丝和形成半导体器件的熔丝的方法。 本发明的方法包括在半导体衬底上形成下面的金属导体，在下面的金属导体上形成绝缘膜，并选择性地蚀刻绝缘膜的区域。 蚀刻绝缘膜的一个区域以形成暴露下面的金属导体的通孔接触区域。 蚀刻第二区域以在用于熔丝金属的绝缘膜中形成凹槽。 金属被埋在绝缘膜和通孔接触区域的第二蚀刻区域内，以分别形成熔丝金属图案和通孔接触金属层。

公开(公告)号：US09042740B2

公开(公告)日：2015-05-26

申请号：US13490022

申请日：2012-06-06

申请人： Young-Tak Han ,  Jang Uk Shin ,  Sang Ho Park ,  Oh Kee Kwon ,  Dong-Hun Lee ,  Yongsoon Baek

发明人： Young-Tak Han ,  Jang Uk Shin ,  Sang Ho Park ,  Oh Kee Kwon ,  Dong-Hun Lee ,  Yongsoon Baek

IPC分类号： H04B10/04 ,  H04B10/12 ,  H04B10/50 ,  G02B6/42 ,  H04B1/04

CPC分类号： G02B6/4201 ,  H03F3/24 ,  H04B2001/0408

摘要： Disclosed is a transmitter optical module which includes a first package generating an optical signal; a second package bonded with the first package by using chip-to-chip bonding, having a silicon optical circuit platform structure, and amplifying the optical signal; and an optical waveguide forming a transmission path of the optical signal from the first package to the second package.

摘要翻译： 公开了一种发射机光学模块，其包括产生光信号的第一封装; 通过使用芯片到芯片接合与第一封装结合的第二封装，具有硅光电路平台结构，并放大光信号; 以及光波导，其形成从第一封装到第二封装的光信号的传输路径。

公开(公告)号：US08804510B2

公开(公告)日：2014-08-12

申请号：US13339739

申请日：2011-12-29

申请人： Dong-Hun Lee ,  Hyunduk Kang

发明人： Dong-Hun Lee ,  Hyunduk Kang

IPC分类号： H04L12/28 ,  H04W4/00 ,  H04J3/16 ,  G06F15/173

CPC分类号： H04L12/2865 ,  H04W28/18 ,  H04W48/08 ,  H04W48/16 ,  H04W72/00

摘要： A system for managing resources in a communication system including systems which do not have a permission for a first frequency band includes a coexistence manager configured to, when a frequency band available for the systems is searched from the first frequency band, manage the systems for coexistence and frequency sharing of the systems in the available frequency band; a coexistence enabler configured to transmit and receive information of the systems and information of the coexistence manager; and a coexistence discovery and information server configured to support control of the coexistence manager over the systems, wherein a plurality of coexistence managers are provided to respectively correspond to the plurality of systems, and wherein, among the plurality of coexistence managers, a first coexistence manager performs a negotiation procedure with coexistence managers neighboring to it, on the basis of one of an etiquette mode, a round-robin mode and a competition mode.

摘要翻译： 用于管理包括不具有第一频带许可的系统的通信系统中的资源的系统包括：共处理管理器，被配置为当从第一频带搜索可用于系统的频带时，管理共存的系统 和可用频带中系统的频率共享; 配置为传送和接收系统的信息和共存管理器的信息的共存使能器; 以及共存发现和信息服务器，被配置为支持通过所述系统对所述共存管理器的控制，其中提供多个共存管理器以分别对应于所述多个系统，并且其中在所述多个共存管理器中，第一共存管理器 基于礼仪模式，循环模式和竞赛模式之一，与其相邻的共存管理器执行协商过程。

公开(公告)号：US08755275B2

公开(公告)日：2014-06-17

申请号：US13339712

申请日：2011-12-29

申请人： Hyunduk Kang ,  Dong-Hun Lee

发明人： Hyunduk Kang ,  Dong-Hun Lee

IPC分类号： H04L12/28 ,  H04W4/00 ,  H04J3/16 ,  G06F15/173

CPC分类号： H04W16/14 ,  H04W72/082

摘要： A system for managing resources in a communication system including systems, which do not have a permission for a first frequency band, includes coexistence managers configured to, when a frequency band available for the systems is searched from the first frequency band, manage the systems for coexistence and frequency sharing of the systems in the available frequency band; a coexistence enabler configured to transmit and receive information of the systems and information of the coexistence managers; and a coexistence discovery and information server configured to support control of the coexistence managers over the systems, wherein predetermined messages are transmitted and received among the coexistence discovery and information server, the coexistence managers and the coexistence enabler to perform a registration procedure, a coexistence information gathering procedure, a coexistence decision making procedure, a reconfiguration procedure, a management procedure and an event procedure, for the coexistence and frequency sharing of the systems.

摘要翻译： 一种用于管理包括不具有第一频带许可的系统的通信系统中的资源的系统包括共存管理器，其被配置为当从第一频带搜索可用于系统的频带时，管理系统 可用频带中系统的共存和频率共享; 一个共存使能器被配置为传送和接收系统的信息和共存管理者的信息; 以及共存发现和信息服务器，其被配置为支持对系统的共存管理器的控制，其中在共存发现和信息服务器之间发送和接收预定消息，共存管理器和共存启动器执行注册过程，共存信息 收集程序，共存决策程序，重新配置程序，管理程序和事件程序，用于系统的共存和频率共享。

公开(公告)号：US08623714B2

公开(公告)日：2014-01-07

申请号：US12728488

申请日：2010-03-22

申请人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

发明人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

IPC分类号： H01L21/00

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/76895 ,  H01L29/665 ,  H01L29/6659

摘要： The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

摘要翻译： 本公开提供了形成电气装置的方法。 该方法可以从衬底上形成栅极结构开始，其中间隔物直接与栅极结构的侧壁接触。 源极区和漏极区形成在衬底中。 在栅极结构上形成金属半导体合金，间隔物的外侧壁和源极区域和漏极区域中的一个。 在金属半导体合金上形成层间电介质层。 通过金属半导体合金上的层间电介质停止形成通孔。 在通孔中的金属半导体合金形成互连。 本公开还包括通过上述方法制造的结构。