公开(公告)号：US20130019032A1

公开(公告)日：2013-01-17

申请号：US13543357

申请日：2012-07-06

Applicant: Dong-Ku HAN ,  Kang-Min LEE ,  Kyung-Ha LEE

Inventor： Dong-Ku HAN ,  Kang-Min LEE ,  Kyung-Ha LEE

IPC: G06F13/28 ,  G06F13/24

CPC classification number: G06F13/24 ,  G06F13/28

Abstract: A method for generating an interrupt signal in a memory controller and supporting a multi-processor is provided. Whether an access for a determined memory region occurs is determined. When the access for the determined memory region occurs, whether the access for the determined memory region has a right is determined. When the access for the determined memory region has the right, a core that will generate an interrupt signal is determined. The determined core is requested to generate the interrupt signal.

Abstract translation: 提供了一种用于在存储器控制器中产生中断信号并支持多处理器的方法。 确定是否存在确定的存储区域的访问。 当确定的存储器区域的访问出现时，确定所确定的存储器区域的存取是否具有权利。 当所确定的存储器区域的访问权限为正确时，确定产生中断信号的核心。 请求确定的内核产生中断信号。

公开(公告)号：US20120102345A1

公开(公告)日：2012-04-26

申请号：US13276503

申请日：2011-10-19

Applicant: Tae-Hong PARK ,  Ji-Yong YOON ,  Kang-Min LEE ,  Yun-Ju KWON ,  Jong-Hyuck HONG

Inventor： Tae-Hong PARK ,  Ji-Yong YOON ,  Kang-Min LEE ,  Yun-Ju KWON ,  Jong-Hyuck HONG

IPC: G06F1/00

CPC classification number: G06F1/324 ,  G06F1/3215 ,  G06F1/3228 ,  G06F1/3253 ,  Y02D10/126 ,  Y02D10/151

Abstract: An apparatus and method for adaptively changing clock frequencies of a Central Processing Unit (CPU) and a bus in a digital system are provided. The system includes an Adaptive Frequency Scaling (AFS) controller and a clock controller. The AFS controller determines whether to change a clock frequency of the CPU according to operation information of the CPU, and determines whether to change a clock frequency of the bus according to operation information of the bus. The clock controller generates a clock frequency of the CPU and a clock frequency of the bus according to the determination of the AFS controller.

Abstract translation: 提供一种用于在数字系统中自适应地改变中央处理单元（CPU）和总线的时钟频率的装置和方法。 该系统包括自适应频率缩放（AFS）控制器和时钟控制器。 AFS控制器根据CPU的操作信息确定是否改变CPU的时钟频率，并根据总线的操作信息确定是否改变总线的时钟频率。 时钟控制器根据AFS控制器的确定产生CPU的时钟频率和总线的时钟频率。

公开(公告)号：US20090044038A1

公开(公告)日：2009-02-12

申请号：US12188481

申请日：2008-08-08

Applicant: Kang-Min LEE

Inventor： Kang-Min LEE

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F9/3861 ,  G06F9/3869 ,  Y02D10/126

Abstract: An apparatus and method for dynamically controlling a clock signal in a pipeline system are provided. In the apparatus and method, a clock generator outputs the clock signal at every period, a PDR is included with each stage for outputting information about a processing speed of each stage, and a CCU controls the delay of the clock signal using the processing time of each stage received from the PDR and providing the clock signal with the controlled delay to a register between stages. Accordingly, the clock signal is dynamically controlled to provide higher operating speeds.

Abstract translation: 提供了一种用于动态控制管道系统中的时钟信号的装置和方法。 在该装置和方法中，时钟发生器以每个周期输出时钟信号，每个级包括PDR，用于输出关于每一级的处理速度的信息，CCU使用处理时间来控制时钟信号的延迟 每个级从PDR接收并且将具有受控延迟的时钟信号提供给级之间的寄存器。 因此，时钟信号被动态地控制以提供更高的操作速度。

公开(公告)号：US20110106992A1

公开(公告)日：2011-05-05

申请号：US12938561

申请日：2010-11-03

Applicant: Kang-Min LEE ,  Ji-Yong YOON

Inventor： Kang-Min LEE ,  Ji-Yong YOON

IPC: G06F13/00

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  Y02D10/126 ,  Y02D10/151

Abstract: An apparatus and a method for scaling a dynamic bus clock are provided. The apparatus for scaling the dynamic bus clock includes at least one master module, at least one slave module, a bus for delivering data transmitted and received by the at least one master module and the at least one slave module, a bus frequency controller for determining a bus clock frequency by considering activity information of the at least one master module, and a clock generator for generating the frequency as determined by the bus frequency controller and providing the generated frequency to the at least one master module, the at least one slave module, and the bus.

Abstract translation: 提供了一种用于缩放动态总线时钟的装置和方法。 用于缩放动态总线时钟的装置包括至少一个主模块，至少一个从模块，用于传送由至少一个主模块和至少一个从模块发送和接收的数据的总线，总线频率控制器，用于确定 通过考虑至少一个主模块的活动信息的总线时钟频率，以及用于产生由总线频率控制器确定的频率并将生成的频率提供给至少一个主模块的时钟发生器，所述至少一个从模块 ，和公共汽车。

公开(公告)号：US20080180288A1

公开(公告)日：2008-07-31

申请号：US12021730

申请日：2008-01-29

Applicant: Kang-Min LEE

Inventor： Kang-Min LEE

IPC: H03M9/00

CPC classification number: H03M9/00 ,  H04L25/49

Abstract: Disclosed is a method and a system for transmitting/receiving serial data efficiently by minimizing the transitions of bits in a serial communication system, as well as a serial communication system for the same. The method for converting coded parallel data into serial data and transmitting the serial data in a serial communication system includes determining a position, in which an information bit of the coded parallel data is found first, the information bit being defined as a bit having a predetermined bit value so that the information bit is not compressed; and serially transmitting the information bit found first and at least one bit following the information bit found first as compressed serial data until the determined position is reached.

Abstract translation: 公开了一种通过使串行通信系统中的位的转换最小化以及用于串行通信系统的串行通信系统来有效发送/接收串行数据的方法和系统。 用于将编码的并行数据转换为串行数据并在串行通信系统中发送串行数据的方法包括：确定首先找到编码的并行数据的信息位的位置，该信息位被定义为具有预定的 位值，使得信息位不被压缩; 并且首先发送首先找到的信息位和首先被找到的信息位之后的至少一个位作为压缩串行数据直到达到确定的位置。