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    Semiconductor devices including trench isolation structures and methods of forming the same
    1.
    发明申请
    Semiconductor devices including trench isolation structures and methods of forming the same 审中-公开
    包括沟槽隔离结构的半导体器件及其形成方法

    公开(公告)号：US20070059898A1

    公开(公告)日：2007-03-15

    申请号：US11393546

    申请日：2006-03-30

    申请人： Dong-Suk Shin ,  Seung-Jin Lee ,  Yong-Kuk Jeong ,  Ki-Kwan Park

    发明人： Dong-Suk Shin ,  Seung-Jin Lee ,  Yong-Kuk Jeong ,  Ki-Kwan Park

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L21/76232

    摘要： Trench isolation methods include forming a first trench and a second trench, having a larger width than the first trench, in a semiconductor substrate. A lower isolation layer is formed having a first thickness on an upper sidewall of the first trench and a second thickness on an upper sidewall of the second trench using a first high density plasma deposition process, the second thickness being greater than the first thickness. An upper isolation layer is formed on the semiconductor substrate including the lower isolation layer using a second high density plasma deposition process, different from the first high density plasma deposition process. The first and second high density plasma deposition processes may be chemical vapor deposition processes. Semiconductor devices including a trench isolation structure are also provided.

    摘要翻译： 沟槽隔离方法包括在半导体衬底中形成具有比第一沟槽更大的宽度的第一沟槽和第二沟槽。 使用第一高密度等离子体沉积工艺在第一沟槽的上侧壁上形成具有第一厚度的第一厚度和在第二沟槽的上侧壁上的第二厚度的下隔离层，第二厚度大于第一厚度。 使用不同于第一高密度等离子体沉积工艺的第二高密度等离子体沉积工艺在包括下隔离层的半导体衬底上形成上隔离层。 第一和第二高密度等离子体沉积工艺可以是化学气相沉积工艺。 还提供了包括沟槽隔离结构的半导体器件。

    Method of forming interconnection lines for semiconductor device
    2.
    发明授权
    Method of forming interconnection lines for semiconductor device 失效
    形成半导体器件互连线的方法

    公开(公告)号：US07192864B2

    公开(公告)日：2007-03-20

    申请号：US11049730

    申请日：2005-02-04

    申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

    发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/02063 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76835

    摘要： The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

    摘要翻译： 本发明公开了一种制造用于半导体器件的互连线的方法。 该方法包括在半导体衬底上形成层间绝缘层。 通过层间绝缘层形成通孔。 形成通孔填充材料以填充通孔。 在通孔填充材料上形成光致抗蚀剂图案。 使用光致抗蚀剂图案作为蚀刻掩模对通孔填充材料和层间绝缘层进行各向异性蚀刻以形成沟槽。 使用两次湿式蚀刻工艺去除通孔填充材料的剩余部分。 在去除通孔填充材料的剩余部分之后，在通孔和沟槽中形成导电层图案。

    Method of forming interconnection lines for semiconductor device
    4.
    发明申请
    Method of forming interconnection lines for semiconductor device 失效
    形成半导体器件互连线的方法

    公开(公告)号：US20050176236A1

    公开(公告)日：2005-08-11

    申请号：US11049730

    申请日：2005-02-04

    申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

    发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

    IPC分类号： H01L21/3205 ,  H01L21/02 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/02063 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76835

    摘要： The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

    摘要翻译： 本发明公开了一种制造用于半导体器件的互连线的方法。 该方法包括在半导体衬底上形成层间绝缘层。 通过层间绝缘层形成通孔。 形成通孔填充材料以填充通孔。 在通孔填充材料上形成光致抗蚀剂图案。 使用光致抗蚀剂图案作为蚀刻掩模对通孔填充材料和层间绝缘层进行各向异性蚀刻以形成沟槽。 使用两次湿式蚀刻工艺去除通孔填充材料的剩余部分。 在去除通孔填充材料的剩余部分之后，在通孔和沟槽中形成导电层图案。

    Method of forming dual damascene interconnection using low-k dielectric material
    6.
    发明授权
    Method of forming dual damascene interconnection using low-k dielectric material 有权
    使用低k介电材料形成双镶嵌互连的方法

    公开(公告)号：US07022600B2

    公开(公告)日：2006-04-04

    申请号：US10437806

    申请日：2003-05-14

    申请人： Jae-Hak Kim ,  Soo-Geun Lee ,  Ki-Kwan Park ,  Kyoung-Woo Lee

    发明人： Jae-Hak Kim ,  Soo-Geun Lee ,  Ki-Kwan Park ,  Kyoung-Woo Lee

    IPC分类号： H01L21/475

    CPC分类号： H01L21/76811 ,  H01L21/76808 ,  H01L21/76813

    摘要： In order to avoid a faulty pattern resulting from a photoresist tail being formed due to a step difference of an upper hard mask layer when a dual hard mask layer is used, a planarization layer is formed following patterning of the upper hard mask layer. In this manner, a photoresist pattern is formed without the creation of a photoresist tail. Alternatively, a single hard mask layer and a planarization layer are substituted for the dual lower hard mask layer and an upper hard mask layer, respectively. In this manner, it is therefore possible to form a photoresist pattern without a photoresist tail being formed during photolithographic processes. In order to prevent formation of a facet, the planarization layer is thickly formed or, alternatively, the hard mask layer is etched using the photoresist pattern.

    摘要翻译： 为了避免当使用双硬掩模层时由于上部硬掩模层的阶差而形成的光致抗蚀剂尾部产生的故障图案，在上部硬掩模层的图案化之后形成平坦化层。 以这种方式，形成光致抗蚀剂图案而不产生光致抗蚀剂尾部。 或者，单个硬掩模层和平坦化层分别代替双下硬掩模层和上硬掩模层。 以这种方式，因此可以在光刻工艺期间形成光致抗蚀剂图案而不形成光致抗蚀剂尾部。 为了防止小面的形成，平坦化层被厚地形成，或者使用光致抗蚀剂图案蚀刻硬掩模层。