公开(公告)号：US20100240323A1

公开(公告)日：2010-09-23

申请号：US12407700

申请日：2009-03-19

申请人： Dongjiang Qiao ,  Frederic Bossu

发明人： Dongjiang Qiao ,  Frederic Bossu

IPC分类号： H04B1/40 ,  H03B19/00

CPC分类号： G06F1/06 ,  H03K23/667 ,  H03K23/68

摘要： A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal.

摘要翻译： 描述了可以将时钟信号分频并提供具有良好信号特性的差分输出信号的同步分频器。 在一个示例性设计中，同步分频器包括单端分频器和同步电路。 单端分频器分频时钟信号，并提供第一和第二单端信号，这可能是具有定时偏移的互补信号。 同步电路基于时钟信号重新采样第一和第二单端信号，并提供具有减小的定时偏差的差分输出信号。 在一个示例性设计中，同步电路包括第一和第二开关以及第一和第二逆变器。 第一开关和第一反相器形成第一采样保持电路或重新采样第一单端信号的第一锁存器。 第二开关和第二反相器形成第二采样保持电路或重新采样第二单端信号的第二锁存器。

公开(公告)号：US08344765B2

公开(公告)日：2013-01-01

申请号：US12836454

申请日：2010-07-14

申请人： Dongjiang Qiao ,  Frederic Bossu

发明人： Dongjiang Qiao ,  Frederic Bossu

IPC分类号： H03B19/06 ,  H03K21/00

CPC分类号： H03K23/40 ,  H03K21/00

摘要： A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio.

摘要翻译： 公开了一种使用可配置分频比对信号频率进行分频的方法。 具有第一频率的输入信号在具有可配置分频比的分频器中的时钟开关处被接收。 操作分频器内的非时钟开关可以选择多个分频比之一。 输出信号以第一频率除以选择的分频比的第二频率输出。

公开(公告)号：US08265568B2

公开(公告)日：2012-09-11

申请号：US12407700

申请日：2009-03-19

申请人： Dongjiang Qiao ,  Frederic Bossu

发明人： Dongjiang Qiao ,  Frederic Bossu

IPC分类号： H03K25/00

CPC分类号： G06F1/06 ,  H03K23/667 ,  H03K23/68

摘要： A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal.

摘要翻译： 描述了可以将时钟信号分频并提供具有良好信号特性的差分输出信号的同步分频器。 在一个示例性设计中，同步分频器包括单端分频器和同步电路。 单端分频器分频时钟信号，并提供第一和第二单端信号，这可能是具有定时偏移的互补信号。 同步电路基于时钟信号重新采样第一和第二单端信号，并提供具有减小的定时偏差的差分输出信号。 在一个示例性设计中，同步电路包括第一和第二开关以及第一和第二逆变器。 第一开关和第一反相器形成第一采样保持电路或重新采样第一单端信号的第一锁存器。 第二开关和第二反相器形成第二采样保持电路或重新采样第二单端信号的第二锁存器。

公开(公告)号：US20110012647A1

公开(公告)日：2011-01-20

申请号：US12836454

申请日：2010-07-14

申请人： Dongjiang Qiao ,  Frederic Bossu

发明人： Dongjiang Qiao ,  Frederic Bossu

IPC分类号： H03B19/00

CPC分类号： H03K23/40 ,  H03K21/00

摘要： A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio.

摘要翻译： 公开了一种使用可配置分频比对信号频率进行分频的方法。 具有第一频率的输入信号在具有可配置分频比的分频器中的时钟开关处被接收。 操作分频器内的非时钟开关可以选择多个分频比之一。 输出信号以第一频率除以选择的分频比的第二频率输出。

公开(公告)号：US08791740B2

公开(公告)日：2014-07-29

申请号：US12724337

申请日：2010-03-15

申请人： Dongjiang Qiao ,  Bhushan S. Asuri ,  Junxiong Deng ,  Frederic Bossu

发明人： Dongjiang Qiao ,  Bhushan S. Asuri ,  Junxiong Deng ,  Frederic Bossu

IPC分类号： H03K3/289

CPC分类号： H04B1/408 ,  H03B19/00 ,  H03L7/0812 ,  H04B1/109

摘要： A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with an input signal to produce a first mixed output. Output from the slave frequency divider is mixed with the input signal to produce a second mixed output. The second mixed output is forced to be in phase with the first mixed output.

摘要翻译： 公开了一种用于降低本地振荡器（LO）路径中的平均电流消耗的方法。 在主分频器和从分频器处接收LO信号。 主分频器的输出与输入信号混合，产生第一个混合输出。 来自从分频器的输出与输入信号混合，产生第二个混合输出。 第二个混合输出被强制与第一个混合输出同相。

公开(公告)号：US07825703B2

公开(公告)日：2010-11-02

申请号：US12193693

申请日：2008-08-18

申请人： Dongjiang Qiao ,  Frederic Bossu

发明人： Dongjiang Qiao ,  Frederic Bossu

IPC分类号： H03B19/00

CPC分类号： H03L7/183 ,  H03H11/265 ,  H03K23/42 ,  H03L7/0812

摘要： A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q) that differ from each other in phase by ninety degrees. To divide by three, the frequency divider includes a divide-by-three frequency divider. The divide-by-three frequency divider includes a divide-by-three circuit, a delay circuit, and a feedback circuit. The divide-by-three circuit frequency divides a signal from the VCO and generates therefrom three signals C, A′ and B that differ from each other in phase by one hundred twenty degrees. The delay circuit delays signal A′ to generate a delayed version A of the signal A′. The feedback circuit controls the delay circuit such that the delayed version A (I) is ninety degrees out of phase with respect to the signal C (Q).

摘要翻译： 本地振荡器包括耦合到VCO的输出的可编程分频器。 分频器可以设置为三分频。 除了除数以外，分频器输出相位相差九十度的正交信号（I，Q）。 为了除以3，分频器包括一个除以三分频器。 除以三分频器包括三分之一电路，延迟电路和反馈电路。 三分频电路分频来自VCO的信号，从而产生三相彼此相差一百二十度的信号C，A'和B。 延迟电路延迟信号A'以产生信号A'的延迟版本A. 反馈电路控制延迟电路，使得延迟版本A（I）相对于信号C（Q）相差90度。

公开(公告)号：US20110012648A1

公开(公告)日：2011-01-20

申请号：US12724337

申请日：2010-03-15

申请人： Dongjiang Qiao ,  Bhushan S. Asuri ,  Junxiong Deng ,  Frederic Bossu

发明人： Dongjiang Qiao ,  Bhushan S. Asuri ,  Junxiong Deng ,  Frederic Bossu

IPC分类号： H03L7/00

CPC分类号： H04B1/408 ,  H03B19/00 ,  H03L7/0812 ,  H04B1/109

摘要： A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with an input signal to produce a first mixed output. Output from the slave frequency divider is mixed with the input signal to produce a second mixed output. The second mixed output is forced to be in phase with the first mixed output.

摘要翻译： 公开了一种用于降低本地振荡器（LO）路径中的平均电流消耗的方法。 在主分频器和从分频器处接收LO信号。 主分频器的输出与输入信号混合，产生第一个混合输出。 来自从分频器的输出与输入信号混合，产生第二个混合输出。 第二个混合输出被强制与第一个混合输出同相。

公开(公告)号：US20100039153A1

公开(公告)日：2010-02-18

申请号：US12193693

申请日：2008-08-18

申请人： Dongjiang Qiao ,  Frederic Bossu

发明人： Dongjiang Qiao ,  Frederic Bossu

IPC分类号： H03H11/16

CPC分类号： H03L7/183 ,  H03H11/265 ,  H03K23/42 ,  H03L7/0812

摘要： A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q) that differ from each other in phase by ninety degrees. To divide by three, the frequency divider includes a divide-by-three frequency divider. The divide-by-three frequency divider includes a divide-by-three circuit, a delay circuit, and a feedback circuit. The divide-by-three circuit frequency divides a signal from the VCO and generates therefrom three signals C, A′ and B that differ from each other in phase by one hundred twenty degrees. The delay circuit delays signal A′ to generate a delayed version A of the signal A′. The feedback circuit controls the delay circuit such that the delayed version A (I) is ninety degrees out of phase with respect to the signal C (Q).

摘要翻译： 本地振荡器包括耦合到VCO的输出的可编程分频器。 分频器可以设置为三分频。 除了除数以外，分频器输出相位相差九十度的正交信号（I，Q）。 为了除以3，分频器包括一个除以三分频器。 除以三分频器包括三分之一电路，延迟电路和反馈电路。 三分频电路分频来自VCO的信号，从而产生三相彼此相差一百二十度的信号C，A'和B。 延迟电路延迟信号A'以产生信号A'的延迟版本A. 反馈电路控制延迟电路，使得延迟版本A（I）相对于信号C（Q）相差90度。

公开(公告)号：US08570076B2

公开(公告)日：2013-10-29

申请号：US12829107

申请日：2010-07-01

申请人： Gary L. Brown ,  Alberto Cicalini ,  Dongjiang Qiao

发明人： Gary L. Brown ,  Alberto Cicalini ,  Dongjiang Qiao

IPC分类号： H03B19/06

CPC分类号： H03L7/00 ,  H03K23/667 ,  H03K23/68

摘要： A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second portion is communicated to the latch. The divider generates a frequency divided enable signal that is communicated to the latch. The latch generates a divided down output signal based on the oscillating input signal and the enable signal. The output signal is insensitive to phase noise present on the enable signal as long as the phase noise on the enable signal is less than one-half of the period of oscillation of the oscillating input signal. Because the noise generated by the low power frequency divider is not propagated to the output signal generated by the PPFD, the PPFD generates low noise, frequency divided signals with relatively low power consumption.

摘要翻译： 并行路径分频器（PPFD）包括低功耗分频器和高速锁存器。 存在于PPFD的输入节点上的振荡输入信号的第一部分被传送到分频器，并且第二部分被传送到锁存器。 分频器产生与锁存器通信的分频使能信号。 锁存器基于振荡输入信号和使能信号产生分频输出信号。 输出信号对使能信号中存在的相位噪声不敏感，只要使能信号的相位噪声小于振荡输入信号的振荡周期的一半即可。 由于低功耗分频器产生的噪声不会传播到由PPFD产生的输出信号，所以PPFD产生低噪声，分频信号，功耗相对较低。

公开(公告)号：US20120001666A1

公开(公告)日：2012-01-05

申请号：US12829107

申请日：2010-07-01

申请人： Gary L. Brown ,  Alberto Cicalini ,  Dongjiang Qiao

发明人： Gary L. Brown ,  Alberto Cicalini ,  Dongjiang Qiao

IPC分类号： H03B19/06

CPC分类号： H03L7/00 ,  H03K23/667 ,  H03K23/68

摘要： A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second portion is communicated to the latch. The divider generates a frequency divided enable signal that is communicated to the latch. The latch generates a divided down output signal based on the oscillating input signal and the enable signal. The output signal is insensitive to phase noise present on the enable signal as long as the phase noise on the enable signal is less than one-half of the period of oscillation of the oscillating input signal. Because the noise generated by the low power frequency divider is not propagated to the output signal generated by the PPFD, the PPFD generates low noise, frequency divided signals with relatively low power consumption.

摘要翻译： 并行路径分频器（PPFD）包括低功耗分频器和高速锁存器。 存在于PPFD的输入节点上的振荡输入信号的第一部分被传送到分频器，并且第二部分被传送到锁存器。 分频器产生与锁存器通信的分频使能信号。 锁存器基于振荡输入信号和使能信号产生分频输出信号。 输出信号对使能信号中存在的相位噪声不敏感，只要使能信号的相位噪声小于振荡输入信号的振荡周期的一半即可。 由于低功耗分频器产生的噪声不会传播到由PPFD产生的输出信号，所以PPFD产生低噪声，分频信号，功耗相对较低。