公开(公告)号：US07405977B2

公开(公告)日：2008-07-29

申请号：US11474430

申请日：2006-06-26

申请人： Doo-Sub Lee ,  Heung-Soo Lim

发明人： Doo-Sub Lee ,  Heung-Soo Lim

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select one of the rows and drive the selected row with a word line voltage, and voltage lines transmitting the respective read voltages to the row selecting circuit as the word line voltage. The read voltages are supplied to the respective voltage lines before starting read periods of the multi-bit read operation.

摘要翻译： 闪速存储器件包括排列成行和列的存储单元的阵列和适于在多位读取操作期间同时产生多个读取电压的字线电压产生电路。 该装置还包括行选择电路，其适于选择一行中的一行并用字线电压驱动所选择的行，以及电压线将各个读电压传送到行选择电路作为字线电压。 在开始多位读取操作的读取周期之前，读取电压被提供给各个电压线。

公开(公告)号：US20070047300A1

公开(公告)日：2007-03-01

申请号：US11474430

申请日：2006-06-26

申请人： Doo-Sub Lee ,  Heung-Soo Lim

发明人： Doo-Sub Lee ,  Heung-Soo Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select one of the rows and drive the selected row with a word line voltage, and voltage lines transmitting the respective read voltages to the row selecting circuit as the word line voltage. The read voltages are supplied to the respective voltage lines before starting read periods of the multi-bit read operation.

摘要翻译： 闪速存储器件包括排列成行和列的存储单元的阵列和适于在多位读取操作期间同时产生多个读取电压的字线电压产生电路。 该装置还包括行选择电路，其适于选择一行中的一行并用字线电压驱动所选择的行，以及电压线将各个读电压传送到行选择电路作为字线电压。 在开始多位读取操作的读取周期之前，读取电压被提供给各个电压线。

公开(公告)号：US20080049499A1

公开(公告)日：2008-02-28

申请号：US11563966

申请日：2006-11-28

申请人： Doo-Sub Lee

发明人： Doo-Sub Lee

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/20 ,  G11C2216/22

摘要： A flash memory device includes: a memory cell array including pluralities of blocks; a block status storage unit including pluralities of latch cells arranged in rows and columns to store block status information signals corresponding to each of the blocks and providing the block status information signals in response to each of the write and read addresses; and a controller regulating an access to the memory cell array in response to the block status information signals. The block status storage unit provides information about whether a read address input during a read-while-write operation or suspend read operation is valid, and offers information about whether a current block is a write block or a write protection block.

摘要翻译： 闪存器件包括：包括多个块的存储单元阵列; 块状态存储单元，包括以行和列排列的多个锁存单元，以存储对应于每个块的块状态信息信号，并且响应于每个写入和读取地址提供块状态信息信号; 以及控制器，其响应于块状态信息信号调节对存储器单元阵列的访问。 块状态存储单元提供关于读写操作或挂起读操作期间输入的读地址是否有效的信息，并提供关于当前块是写块还是写保护块的信息。

公开(公告)号：US07274599B2

公开(公告)日：2007-09-25

申请号：US11320470

申请日：2005-12-29

申请人： Doo-Sub Lee

发明人： Doo-Sub Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/12

摘要： A NOR flash memory device configured to perform a program operation using an ISPP scheme, and comprising a plurality of memory cells, a word line voltage generator, and a scan controller is provided. A method of programming the NOR flash memory device comprising a bit scan method is also provided. The maximum number of cells that may be programmed simultaneously in the bit scan method is indicated by a scan bit number. The scan bit number may be changed by the scan controller during the program operation.

摘要翻译： 一种NOR闪存器件，被配置为使用ISPP方案执行编程操作，并且包括多个存储器单元，字线电压发生器和扫描控制器。 还提供了一种编程包括位扫描方法的NOR闪存器件的方法。 在位扫描方法中可以同时编程的单元的最大数目由扫描位数表示。 在编程操作期间扫描控制器可以改变扫描位数。

公开(公告)号：US07428169B2

公开(公告)日：2008-09-23

申请号：US11262759

申请日：2005-11-01

申请人： Doo-Sub Lee ,  Seung-Keun Lee

发明人： Doo-Sub Lee ,  Seung-Keun Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/30

摘要： A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage generating unit for generating a negative voltage through a first charge pump; and a second voltage generating unit for generating a positive voltage through a second charge pump. During an accelerated programming operation, the first voltage generating unit increases a pumping efficiency of the first charge pump using an external power supply voltage, and the second voltage generating unit directly outputs the external power supply voltage.

摘要翻译： 非易失性半导体存储器件包括多个存储器单元的存储单元阵列; 以及用于产生要施加到存储单元的编程电压的电压产生电路。 电压产生电路包括：第一电压产生单元，用于通过第一电荷泵产生负电压; 以及用于通过第二电荷泵产生正电压的第二电压产生单元。 在加速编程操作期间，第一电压产生单元使用外部电源电压提高第一电荷泵的泵送效率，并且第二电压产生单元直接输出外部电源电压。

公开(公告)号：US20080049493A1

公开(公告)日：2008-02-28

申请号：US11617939

申请日：2006-12-29

申请人： Doo-Sub Lee ,  Jong-In Choi

发明人： Doo-Sub Lee ,  Jong-In Choi

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3477

摘要： A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address for selecting the next word line, whether the incremented address matches one of reference addresses; and varying the post-programming unit of the selected memory cells whenever the incremented address matches one of reference addresses.

摘要翻译： 一种对闪速存储器件进行后编程的方法包括以下步骤：以预定单元对选定字线的存储单元进行后编程; 在增加用于选择下一字线的地址之后，确定递增地址是否匹配参考地址之一; 以及每当所述增加的地址与参考地址之一匹配时，改变所选存储单元的后编程单元。

公开(公告)号：US07460412B2

公开(公告)日：2008-12-02

申请号：US11617939

申请日：2006-12-29

申请人： Doo-Sub Lee ,  Jong-In Choi

发明人： Doo-Sub Lee ,  Jong-In Choi

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C8/00

CPC分类号： G11C16/0416 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3477

摘要： A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address for selecting the next word line, whether the incremented address matches one of reference addresses; and varying the post-programming unit of the selected memory cells whenever the incremented address matches one of reference addresses.

摘要翻译： 一种对闪速存储器件进行后编程的方法包括以下步骤：以预定单元对选定字线的存储单元进行后编程; 在增加用于选择下一字线的地址之后，确定递增地址是否匹配参考地址之一; 以及每当所述增加的地址与参考地址之一匹配时，改变所选存储单元的后编程单元。

公开(公告)号：US07428170B2

公开(公告)日：2008-09-23

申请号：US11604227

申请日：2006-11-27

申请人： Doo-Sub Lee

发明人： Doo-Sub Lee

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/12 ,  G11C5/145

摘要： A voltage generation circuit of a flash memory device includes a high voltage generator, a word line voltage generator, and a column selection voltage switch. The high voltage generator is configured to increase an internal power voltage from a first voltage to a second voltage which is higher than the first voltage. The word line voltage regulator is configured to generate an incremental step pulse based on the internal power voltage, where the incremental step pulse is output as a word line program voltage before the internal power voltage reaches the second voltage. The column selection voltage switch is configured to output a column selection voltage for selecting a bit line based on the internal power voltage.

摘要翻译： 闪存器件的电压产生电路包括高压发生器，字线电压发生器和列选择电压开关。 高电压发生器被配置为将内部电力电压从第一电压增加到高于第一电压的第二电压。 字线电压调节器被配置为基于内部电源电压产生增量步进脉冲，其中在内部电源电压达到第二电压之前，增量步进脉冲作为字线编程电压输出。 列选择电压开关被配置为输出用于基于内部电源电压来选择位线的列选择电压。

公开(公告)号：US07248505B2

公开(公告)日：2007-07-24

申请号：US10954255

申请日：2004-09-29

申请人： Myong-Jae Kim ,  Doo-Sub Lee

发明人： Myong-Jae Kim ,  Doo-Sub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/3459 ,  G11C16/12

摘要： A flash memory device includes a write driver for driving a data line according to data to be written in a flash memory cell during a program period, a sense amplifier circuit for sensing and amplifying the data stored in the flash memory cell during a program verify period, and an insulation circuit for electrically insulating the sense amplifier circuit from the data line during an operation period of the write driver.

摘要翻译： 闪速存储器件包括用于在程序周期期间根据要写入快闪存储单元的数据驱动数据线的写入驱动器，用于在程序验证周期期间感测和放大存储在闪存单元中的数据的读出放大器电路 以及用于在写入驱动器的操作期间将读出放大器电路与数据线电绝缘的绝缘电路。

公开(公告)号：US20060239078A1

公开(公告)日：2006-10-26

申请号：US11320470

申请日：2005-12-29

申请人： Doo-Sub Lee

发明人： Doo-Sub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A NOR flash memory device configured to perform a program operation using an ISPP scheme, and comprising a plurality of memory cells, a word line voltage generator, and a scan controller is provided. A method of programming the NOR flash memory device comprising a bit scan method is also provided. The maximum number of cells that may be programmed simultaneously in the bit scan method is indicated by a scan bit number. The scan bit number may be changed by the scan controller during the program operation.

摘要翻译： 一种NOR闪存器件，被配置为使用ISPP方案执行编程操作，并且包括多个存储器单元，字线电压发生器和扫描控制器。 还提供了一种编程包括位扫描方法的NOR闪存器件的方法。 在位扫描方法中可以同时编程的单元的最大数目由扫描位数表示。 在编程操作期间扫描控制器可以改变扫描位数。