公开(公告)号：US06946706B1

公开(公告)日：2005-09-20

申请号：US10616381

申请日：2003-07-09

申请人： Douglas Brisbin ,  David Tsuei ,  Alexander H. Owens ,  Andy Strachan

发明人： Douglas Brisbin ,  David Tsuei ,  Alexander H. Owens ,  Andy Strachan

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/4238

摘要： An LDMOS structure which provides for reduced hot carrier effects. The reduction in hot carrier effects is achieved by increasing the size of the drain region of the LDMOS relative to the size of the source region. The larger size of the drain region reduces the concentration of electrons entering the drain region. This reduction in the concentration of electrons reduces the number of impact ionizations, which in turn reduces the hot carrier effects. The overall performance of the LDMOS is improved by reducing the hot carrier effects.

摘要翻译： 提供减少热载体效应的LDMOS结构。 通过增加LDMOS的漏极区域相对于源极区域的尺寸来实现热载流子效应的降低。 漏极区域的较大尺寸减小了进入漏极区域的电子的浓度。 电子浓度的这种降低减少了冲击电离的数量，这又降低了热载流子的影响。 通过减少热载体效应，提高了LDMOS的整体性能。

公开(公告)号：US06586302B1

公开(公告)日：2003-07-01

申请号：US09931477

申请日：2001-08-16

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Chin Miin Shyu ,  David Tsuei ,  Peter Johnson ,  Alexander H. Owens

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Chin Miin Shyu ,  David Tsuei ,  Peter Johnson ,  Alexander H. Owens

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method for making an electrically programmable and erasable memory cell is disclosed. Specifically, a method for creating a floating gate using shallow trench isolation-type techniques is utilized to provide a floating gate having sharply defined tip characteristics. A first insulating layer is formed over a substrate. A conductive material is formed over the first insulating layer. A trench is defined in the conductive layer. This trench is filled with an oxide which is used as a mask to define tips of the floating gate during an etching process which defines the edges of the floating gate. After the floating gate has been etched, a tunneling oxide deposited over the floating gate. A conductive material is then formed over the tunneling oxide.

摘要翻译： 公开了一种制造电可编程和可擦除存储单元的方法。 具体地说，利用浅沟槽隔离型技术产生浮置栅极的方法用于提供具有尖锐定义的尖端特性的浮动栅极。 第一绝缘层形成在衬底上。 在第一绝缘层上形成导电材料。 在导电层中限定沟槽。 该沟槽填充有氧化物，其用作掩模以在限定浮动栅极的边缘的蚀刻工艺期间限定浮置栅极的尖端。 在浮栅被蚀刻之后，沉积在浮栅上的隧道氧化物。 然后在隧道氧化物上形成导电材料。

公开(公告)号：US06548868B1

公开(公告)日：2003-04-15

申请号：US09879415

申请日：2001-06-11

申请人： David Tsuei ,  Vladislav Vashchenko

发明人： David Tsuei ,  Vladislav Vashchenko

IPC分类号： H01L2362

CPC分类号： H01L27/0255

摘要： In a ESD protection clamp, breakdown and triggering voltage of the structure are reduced by introducing an internal zener diode structure that has a lower avalanche breakdown than the p-n junction of the ESD device. This introduces extra holes into the source junction region causing electrons to be injected into the junction and into the drain junction region to increase the carrier multiplication rate to increase the current density and lower the triggering voltage and breakdown voltage of devices such as NMOS devices or LVTSCRs.

摘要翻译： 在ESD保护钳中，通过引入具有比ESD器件的p-n结更低的雪崩击穿的内部齐纳二极管结构来减小结构的击穿和触发电压。 这会在源极结区域引入额外的空穴，导致电子注入到结和漏极结区域，以增加载流子倍增率，以增加电流密度，并降低诸如NMOS器件或LVTSCR之类的器件的触发电压和击穿电压 。