公开(公告)号：US06586302B1

公开(公告)日：2003-07-01

申请号：US09931477

申请日：2001-08-16

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Chin Miin Shyu ,  David Tsuei ,  Peter Johnson ,  Alexander H. Owens

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Chin Miin Shyu ,  David Tsuei ,  Peter Johnson ,  Alexander H. Owens

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method for making an electrically programmable and erasable memory cell is disclosed. Specifically, a method for creating a floating gate using shallow trench isolation-type techniques is utilized to provide a floating gate having sharply defined tip characteristics. A first insulating layer is formed over a substrate. A conductive material is formed over the first insulating layer. A trench is defined in the conductive layer. This trench is filled with an oxide which is used as a mask to define tips of the floating gate during an etching process which defines the edges of the floating gate. After the floating gate has been etched, a tunneling oxide deposited over the floating gate. A conductive material is then formed over the tunneling oxide.

摘要翻译： 公开了一种制造电可编程和可擦除存储单元的方法。 具体地说，利用浅沟槽隔离型技术产生浮置栅极的方法用于提供具有尖锐定义的尖端特性的浮动栅极。 第一绝缘层形成在衬底上。 在第一绝缘层上形成导电材料。 在导电层中限定沟槽。 该沟槽填充有氧化物，其用作掩模以在限定浮动栅极的边缘的蚀刻工艺期间限定浮置栅极的尖端。 在浮栅被蚀刻之后，沉积在浮栅上的隧道氧化物。 然后在隧道氧化物上形成导电材料。

公开(公告)号：US07259411B1

公开(公告)日：2007-08-21

申请号：US10728132

申请日：2003-12-04

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823885 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.

摘要翻译： 垂直MOS晶体管具有垂直堆叠的源极区域，沟道区域和漏极区域以及从漏极区域的顶表面延伸穿过漏极区域，沟道区域并且部分地延伸到源极区域的沟槽 。 垂直MOS晶体管还具有对沟槽进行排列的绝缘层，以及接触绝缘层以填充沟槽的导电栅极区域。

公开(公告)号：US07435628B1

公开(公告)日：2008-10-14

申请号：US11881671

申请日：2007-07-27

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L21/823885 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.

摘要翻译： 垂直MOS晶体管具有垂直堆叠的源极区域，沟道区域和漏极区域以及从漏极区域的顶表面延伸穿过漏极区域，沟道区域并且部分地延伸到源极区域的沟槽 。 垂直MOS晶体管还具有对沟槽进行排列的绝缘层，以及接触绝缘层以填充沟槽的导电栅极区域。

公开(公告)号：US08098121B2

公开(公告)日：2012-01-17

申请号：US12852743

申请日：2010-08-09

申请人： Peter J Hopper ,  Trevor Niblock ,  Peter Johnson ,  Vladislav Vashchenko

发明人： Peter J Hopper ,  Trevor Niblock ,  Peter Johnson ,  Vladislav Vashchenko

IPC分类号： H01H51/22 ,  H01H51/34

CPC分类号： H02M3/34

摘要： A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.

摘要翻译： MEMS磁通开关被制造为铁磁芯。 芯包括中心悬臂，其被制造为可以以其机械和材料性质确定的共振频率振荡的自由梁。 中心悬臂由相关运动振荡器施加的脉冲移动，运动振荡器可以是磁性或电动执行器。

公开(公告)号：US07897472B2

公开(公告)日：2011-03-01

申请号：US12624259

申请日：2009-11-23

申请人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

发明人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

IPC分类号： H01L21/20

CPC分类号： H01L23/645 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/19015 ,  H01L2924/19104 ,  H01L2924/00

摘要： Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils.

摘要翻译： 描述了在半导体晶片上形成多个电感器的方法。 将镀层和光致抗蚀剂层施加在半导体晶片上。 使用光刻技术在光致抗蚀剂层中蚀刻凹陷区域，其暴露下面的镀层的部分。 将金属电镀到光致抗蚀剂层的凹陷区域中以形成多个磁芯电感器构件。 介质绝缘层施加在磁芯电感器部件上。 在电介质绝缘层上施加附加的电镀和光致抗蚀剂层。 在新施加的光致抗蚀剂层中形成凹陷区域。 电镀用于在凹陷区域形成电感线圈。 可选地，可以在电感线圈上施加磁性糊。

公开(公告)号：US07250842B1

公开(公告)日：2007-07-31

申请号：US11200384

申请日：2005-08-09

申请人： Peter Johnson ,  Peter J. Hopper ,  Kyuwoon Hwang ,  Robert Drury

发明人： Peter Johnson ,  Peter J. Hopper ,  Kyuwoon Hwang ,  Robert Drury

IPC分类号： H01F5/00

CPC分类号： H01F41/046 ,  H01F10/14 ,  H01F10/265 ,  H01F17/0033 ,  H01F41/309 ,  H01F2017/0066

摘要： A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.

摘要翻译： 通过利用在磁芯结构周围形成的单个厚的宽的环形环来形成提供单位毫欧范围电阻的非常非常低的电阻微机电系统（MEMS）电感器。 磁芯结构又可以利用具有易轴和硬轴的叠层Ni-Fe结构。

公开(公告)号：US06964907B1

公开(公告)日：2005-11-15

申请号：US10716276

申请日：2003-11-17

申请人： Peter J. Hopper ,  Alexei Sadovnikov ,  Vladislav Vashchenko ,  Peter Johnson

发明人： Peter J. Hopper ,  Alexei Sadovnikov ,  Vladislav Vashchenko ,  Peter Johnson

IPC分类号： H01L21/302 ,  H01L21/306 ,  H01L21/331 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L21/30608 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322

摘要： In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer.

摘要翻译： 在BJT中，通过在外部基极区域和集电极之间形成横向沟槽来减小外部基极到集电极电容。 这通常通过使用<100>取向晶片的<110>方向的各向异性湿蚀刻工艺来完成。

公开(公告)号：US20120161294A1

公开(公告)日：2012-06-28

申请号：US12978492

申请日：2010-12-24

申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

IPC分类号： H01L23/48 ,  H01L23/544 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/0802 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.

摘要翻译： 在每个晶片被形成为包括暴露高精度电路的电路内部的可调节电路元件的开口的过程中，每个具有多个高精度电路和相应的微调控制电路的多个晶片被批量修整。 高精度电路和微调控制电路在修整阶段通过沿着锯木街道行进的金属轨迹进行电激活。 该方法将晶片接触结构连接到每个晶片以电激活金属迹线。 该方法将具有晶片接触结构的晶片放置在当高精度电路的实际输出电压与高精度电路的预测输出电压不匹配时，暴露的可调节电路元件被电镀或阳极化的解决方案中。

公开(公告)号：US20110260248A1

公开(公告)日：2011-10-27

申请号：US12768295

申请日：2010-04-27

申请人： Peter Smeys ,  Peter Johnson ,  Peter J. Hopper ,  William French

发明人： Peter Smeys ,  Peter Johnson ,  Peter J. Hopper ,  William French

IPC分类号： H01L29/786 ,  H01L21/768

CPC分类号： H01L27/1203 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： A silicon-on-insulator (SOI) wafer is formed to have through-the-wafer contacts, and trench based interconnect structures on the back side of the SOI wafer that electrically connect the through-the-wafer contacts. In addition, selected ones of the through-the-wafer contacts bias the bodies of the MOS transistors.

摘要翻译： 形成绝缘体上硅（SOI）晶片以具有贯穿晶片的触点，以及SOI晶片的背侧上的沟槽基互连结构，其电连接晶片间的触点。 此外，通过晶片间接触的选定的一个偏压MOS晶体管的主体。

公开(公告)号：US07875955B1

公开(公告)日：2011-01-25

申请号：US11713921

申请日：2007-03-05

申请人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Philipp Lindorfer

发明人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Philipp Lindorfer

IPC分类号： H01L27/08

CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F17/02 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An on-chip inductor structure for a DC-DC power regulator circuit merges the switching transistor metallization with the inductor. Thick top level conductor metal that is used to strap the transistor array and to lower its on-state resistance is also used to extend the power inductor into the transistor array. Thus, the structure includes three basic components: a power inductor that spirals around the transistor array, the transistor array itself, and the transistor array metallization that is used to form a distributed inductance situated over the transistor array.

摘要翻译： 用于DC-DC功率调节器电路的片上电感器结构将开关晶体管金属化与电感器并入。 用于绑定晶体管阵列并降低其导通电阻的厚顶级导体金属也用于将功率电感器扩展到晶体管阵列中。 因此，该结构包括三个基本部件：围绕晶体管阵列螺旋的功率电感器，晶体管阵列本身以及用于形成位于晶体管阵列上方的分布式电感器的晶体管阵列金属化。