公开(公告)号：US07795126B2

公开(公告)日：2010-09-14

申请号：US11969756

申请日：2008-01-04

申请人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

发明人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L27/14618 ,  H01L23/482 ,  H01L23/4827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

摘要翻译： 本发明的半导体器件包括形成在具有第一和第二表面的半导体衬底上的集成电路和沿着边缘的切口区域。 第一表面包括与集成电路电连接的电接触垫。 半导体衬底的第一表面包括具有延伸超过半导体衬底的边缘的表面部分的顶部保护层。 半导体衬底的第二表面包括具有电连接器的底部保护层。 顶部保护层的表面部分包括与电接触焊盘延伸部电互连的电接触焊盘。 电接触焊盘延伸部经由背面电连接器与电连接器互连，后侧电连接器与形成搭接连接的电接触垫延伸部重叠。 还公开了用于构造这种装置和连接的方法。

公开(公告)号：US5998280A

公开(公告)日：1999-12-07

申请号：US45226

申请日：1998-03-20

申请人： Albert Bergemont ,  Alexander H. Owens

发明人： Albert Bergemont ,  Alexander H. Owens

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/7621 ,  Y10S148/05

摘要： A trench is etched in a silicon substrate covered with an oxide/nitride stack and a field oxide layer is then grown through oxidation of the silicon in the substrate such that the trench is partly filled. There is reduced oxide encroachment into the active areas under the nitride layer because of the partial field oxide growth. Double oxide layers are deposited over the surface of the field oxide layer and the oxide/nitride stack such that the oxide layers fill the remainder of the trench and produce a nearly planar topology. The double oxide layers are then etched back to the nitride layer through chemical mechanical polishing, leaving the field isolation region. After stripping the oxide/nitride stack, a gate oxide layer is grown. A minimal amount of oxide is required to fill the trench because the trench is already almost filled with the field oxide layer and because of the shallow depth of the trench. Consequently, the etch back step causes minimal dishing. Further, the field oxide layer rounds the corner between the trench and the active area, obviating the need for a thin oxide liner in the trench.

摘要翻译： 在被氧化物/氮化物堆叠覆盖的硅衬底中蚀刻沟槽，然后通过衬底中的硅的氧化生长场氧化物层，使得沟槽被部分填充。 由于部分场氧化物生长，氧化物侵蚀减少到氮化物层下面的有源区域中。 双氧化层沉积在场氧化物层和氧化物/氮化物堆叠的表面上，使得氧化物层填充沟槽的其余部分并产生几乎平面的拓扑结构。 然后通过化学机械抛光将双重氧化物层蚀刻回氮化物层，留下场隔离区域。 在剥离氧化物/氮化物堆叠之后，生长栅极氧化物层。 需要最少量的氧化物来填充沟槽，因为沟槽已经几乎被场氧化物层填充，并且由于沟槽的浅深度。 因此，回蚀步骤导致最小的凹陷。 此外，场氧化物层围绕沟槽和有源区域之间的角落，避免了在沟槽中的薄氧化物衬垫的需要。

公开(公告)号：US5045492A

公开(公告)日：1991-09-03

申请号：US411785

申请日：1989-09-25

申请人： Wing K. Huie ,  Alexander H. Owens ,  David S. Pan

发明人： Wing K. Huie ,  Alexander H. Owens ,  David S. Pan

IPC分类号： H01L21/76 ,  H01L21/761 ,  H01L21/8234 ,  H01L21/8249

CPC分类号： H01L21/761 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8249 ,  Y10S148/086

摘要： A method for making an integrated circuit includes forming patches of a silicon nitride mask over the areas where a high-current vertical DMOS and/or NPN transistor, where a vertical NPN transistor and where the NMOS and PMOS transistors of a CMOS pair are to be formed. The nitride mask also includes patches over a network of P-type isolation walls, and two special patches over two special areas at which N+ plugs for the DMOS and NPN transistors are to be formed. A heavy field oxide is grown everywhere except at the nitride patches. The two special patches are selectively removed and by heating and diffusing phosphorous from a POCl.sub.3 source from 950.degree. C. to 1100.degree. C. for at least 30 minutes, two very high conductivity N+ phosphorous plugs are formed through the epitaxial layer at a concentration of over 10.sup.20 phosphorous atoms/cm.sup.3, while the nitride serves to prevent the sensitive channel regions of the DMOS and CMOS transistors from phosphorous doping. This results in close self-alignment of the N+ plugs and their associated DMOS and NPN transistors leading to low on-resistance, to higher IC component density, to a high throughput rate at manufacturing and low cost.

摘要翻译： 制造集成电路的方法包括在高电流垂直DMOS和/或NPN晶体管的区域上形成氮化硅掩模的贴片，其中垂直NPN晶体管和CMOS对的NMOS和PMOS晶体管将成为 形成。 氮化物掩模还包括在P型隔离壁的网络上的贴片，以及两个特殊区域，其中将形成用于DMOS和NPN晶体管的N +插头的两个特殊区域。 除了在氮化物贴片之外，重金属氧化物生长在任何地方。 通过选择性地去除两个特殊的贴片并通过将POCl 3源中的磷从950℃加热并扩散至1100℃至少30分钟，将两个非常高的导电性N +磷塞通过外延层形成，浓度为 超过1020个磷原子/ cm3，而氮化物用于防止DMOS和CMOS晶体管的敏感通道区域进行磷掺杂。 这导致N +插头及其相关的DMOS和NPN晶体管的紧密自对准导致低导通电阻，更高的IC组件密度，在制造时成本高，成本低。

公开(公告)号：US06586302B1

公开(公告)日：2003-07-01

申请号：US09931477

申请日：2001-08-16

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Chin Miin Shyu ,  David Tsuei ,  Peter Johnson ,  Alexander H. Owens

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Chin Miin Shyu ,  David Tsuei ,  Peter Johnson ,  Alexander H. Owens

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method for making an electrically programmable and erasable memory cell is disclosed. Specifically, a method for creating a floating gate using shallow trench isolation-type techniques is utilized to provide a floating gate having sharply defined tip characteristics. A first insulating layer is formed over a substrate. A conductive material is formed over the first insulating layer. A trench is defined in the conductive layer. This trench is filled with an oxide which is used as a mask to define tips of the floating gate during an etching process which defines the edges of the floating gate. After the floating gate has been etched, a tunneling oxide deposited over the floating gate. A conductive material is then formed over the tunneling oxide.

摘要翻译： 公开了一种制造电可编程和可擦除存储单元的方法。 具体地说，利用浅沟槽隔离型技术产生浮置栅极的方法用于提供具有尖锐定义的尖端特性的浮动栅极。 第一绝缘层形成在衬底上。 在第一绝缘层上形成导电材料。 在导电层中限定沟槽。 该沟槽填充有氧化物，其用作掩模以在限定浮动栅极的边缘的蚀刻工艺期间限定浮置栅极的尖端。 在浮栅被蚀刻之后，沉积在浮栅上的隧道氧化物。 然后在隧道氧化物上形成导电材料。

公开(公告)号：US5561319A

公开(公告)日：1996-10-01

申请号：US298041

申请日：1994-08-30

申请人： Alexander H. Owens ,  Shahin Toutounchi ,  Abraham Yee ,  Michael Lyu

发明人： Alexander H. Owens ,  Shahin Toutounchi ,  Abraham Yee ,  Michael Lyu

IPC分类号： H01L23/31 ,  H01L29/06 ,  H01L29/40 ,  H01L29/34 ,  H01L21/265

CPC分类号： H01L29/408 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/3025 ,  Y10S438/953 ,  Y10S438/958

摘要： A CMOS integrated circuit structure is disclosed having a patterned nitride passivation layer, wherein the nitride is patterned such that it does not overlie the thin gate oxide portions of one or more of the MOS devices. When protection against the effects of external radiation is desired, the thin gate oxide areas of the PMOS devices are left uncovered by the patterned nitride passivation layer. When protection is desired against the effects of internally generated "hot electrons", the thin gate oxide areas of the NMOS devices are left uncovered by the patterned nitride passivation layer.

摘要翻译： 公开了具有图案化氮化物钝化层的CMOS集成电路结构，其中图案化氮化物使得其不覆盖一个或多个MOS器件的薄栅极氧化物部分。 当需要防止外部辐射的影响时，PMOS器件的薄栅极氧化物区域被图案化的氮化物钝化层留下。 当需要防止内部产生的“热电子”的影响时，NMOS器件的薄栅极氧化物区域被图案化的氮化物钝化层留下。

公开(公告)号：US5516731A

公开(公告)日：1996-05-14

申请号：US252723

申请日：1994-06-02

申请人： Shahin Toutounchi ,  Abraham Yee ,  Alexander H. Owens ,  Michael Lyu

发明人： Shahin Toutounchi ,  Abraham Yee ,  Alexander H. Owens ,  Michael Lyu

IPC分类号： H01L21/324 ,  H01L21/326 ,  H01L21/8238 ,  H01L21/477

CPC分类号： H01L21/326 ,  H01L21/324 ,  H01L21/8238 ,  Y10S438/953

摘要： A technique for improving the radiation hardness and hot-electron resistance of a CMOS integrated circuit is described whereby undesirable hydrogen ions may be vented through any holes, such as contact holes, in an overlying passivation layer by applying an elevated temperature and/or electrical bias to the integrated circuit die. The elevated temperature and electrical bias serve to accelerate the process by which hydrogen vents from the die. The elimination of unwanted hydrogen significantly reduces threshold shifts in the CMOS integrated circuit, providing greater radiation hardness and hot-electron resistance.

摘要翻译： 描述了一种用于提高CMOS集成电路的辐射硬度和热电子电阻的技术，其中不期望的氢离子可以通过施加升高的温度和/或电偏压而在覆盖的钝化层中通过任何孔（例如接触孔）排出 到集成电路管芯。 升高的温度和电气偏压有助于加速从模具排出氢气的过程。 消除不需要的氢显着降低了CMOS集成电路中的阈值偏移，提供更大的辐射硬度和热电阻。

公开(公告)号：US4706102A

公开(公告)日：1987-11-10

申请号：US795810

申请日：1985-11-07

申请人： David S. Pan ,  Kanak C. Sarma ,  Mark A. Halfacre ,  Alexander H. Owens ,  Brian K. Rosier

发明人： David S. Pan ,  Kanak C. Sarma ,  Mark A. Halfacre ,  Alexander H. Owens ,  Brian K. Rosier

IPC分类号： H01L23/532 ,  H01L29/788 ,  H01L29/78 ,  G11C11/34 ,  H01L27/02 ,  H01L29/04

CPC分类号： H01L23/53271 ,  H01L29/7883 ,  H01L2924/0002

摘要： A memory device, based upon a field effect transistor having a floating gate is constructed for use in a silicon integrated circuit array of similar memory devices. The memory device includes only two polysilicon layers, a portion of each polysilicon layer being connected to each other through a via hole in an intervening silicon dioxide layer to form the floating gate.

公开(公告)号：US4598460A

公开(公告)日：1986-07-08

申请号：US680197

申请日：1984-12-10

申请人： Alexander H. Owens ,  Mark A. Halfacre ,  David S. Pan

发明人： Alexander H. Owens ,  Mark A. Halfacre ,  David S. Pan

IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/265 ,  G11C11/40

CPC分类号： H01L27/11526 ,  H01L21/8238 ,  H01L27/11546 ,  H01L27/105

摘要： A process for making an integrated cirucit EPROM having an array of EPROM devices and CMOS peripheral circuits, including blanket depositions of a first and a second polysilicon layers on a silicon substrate and removing portions of those polysilicon layers. The EPROM floating gate is made from the first polysilicon layer, and the EPROM control gate as well as the P-channel and N-channel gates of the peripheral transistors are all made from the second polysilicon layer. Independently adjustable thresholds for each of the three device types are made possible by forming an N-well at the substrate region at which the P-channel device is to be built, blanket implanting all three channels prior to selectively forming the first polysilicon layer over the EPROM region, and then selectively doping the channels of the N- and P-channel devices only.

摘要翻译： 一种用于制造具有EPROM器件阵列和CMOS外围电路阵列的集成cirucit EPROM的工艺，包括在硅衬底上的第一和第二多晶硅层的覆盖沉积并去除那些多晶硅层的部分。 EPROM浮栅由第一多晶硅层制成，EPROM控制栅极以及外围晶体管的P沟道和N沟道栅都由第二多晶硅层制成。 通过在要构建P沟道器件的衬底区域处形成N阱可以实现三种器件类型中的每一种的独立可调阈值，在选择性地形成第一多晶硅层之前，全面地注入所有三个通道 EPROM区域，然后仅选择性地掺杂N沟道和P沟道器件的沟道。

公开(公告)号：US4590665A

公开(公告)日：1986-05-27

申请号：US680199

申请日：1984-12-10

申请人： Alexander H. Owens ,  Mark A. Halfacre ,  Wing K. Huie ,  David S. Pan

发明人： Alexander H. Owens ,  Mark A. Halfacre ,  Wing K. Huie ,  David S. Pan

IPC分类号： H01L21/22 ,  H01L21/225 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/78 ,  G11C11/40

CPC分类号： H01L27/11526 ,  H01L21/22 ,  H01L21/2253 ,  H01L21/823814 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/7886 ,  Y10S148/082

摘要： A CMOS EPROM or the like is made wherein the basic memory device or EPROM device is an N-channel IGFET (insulated gate field effect transistor) having a control gate self-aligned with an underlying floating gate. The sources and drains of the EPROM devices as well as the sources and drains of peripheral N-channel transistors, are made by implanting with arsenic and with phosphorous. When heated, the faster diffusing phosphorous outruns, and extends from the bulk of, the arsenic so that these sources and drains extend slightly under the adjacent gate. This extension of the drain in the memory device enables a faster programming capability. A similar but oppositely directed lateral extension of all these sources and drains reduces the leakage to the substrate and reduces the chances of shorts to the substrate due to slightly misaligned metal to source and drain contacts.

摘要翻译： 制造CMOS EPROM等，其中基本存储器件或EPROM器件是具有与底层浮置栅极自对准的控制栅极的N沟道IGFET（绝缘栅场效应晶体管）。 EPROM器件的源极和漏极以及外围N沟道晶体管的源极和漏极通过用砷和磷进行注入而制成。 当加热时，较快的扩散磷超出，并从砷的大部分延伸，使得这些源和漏极在相邻栅极下方稍微延伸。 存储器件中漏极的这种扩展使得能够实现更快的编程能力。 所有这些源和漏极的类似但相反导向的横向延伸减少了衬底的泄漏，并且由于稍微不对准金属到源极和漏极接触而减小了衬底短路的机会。

公开(公告)号：US06579777B1

公开(公告)日：2003-06-17

申请号：US08587417

申请日：1996-01-16

申请人： Ting P. Yen ,  Pamela S. Trammel ,  Philippe Schoenborn ,  Alexander H. Owens

发明人： Ting P. Yen ,  Pamela S. Trammel ,  Philippe Schoenborn ,  Alexander H. Owens

IPC分类号： H01L2176

CPC分类号： H01L21/7621

摘要： A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10° and about 75° as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.

摘要翻译： 一种通过在硅衬底中设置开口的方式形成局部氧化的方法，所述局部氧化具有缩小的鸟嘴刺入半导体器件中，所述开口具有从所述凹部开口的垂直轴线测量的具有约10°至约75°之间的锥度的倾斜侧壁， 然后在锥形凹槽开口内生长场氧化物以形成局部氧化。