Unordered load/store queue
    1.
    发明授权
    Unordered load/store queue 有权
    无序的加载/存储队列

    公开(公告)号:US08447911B2

    公开(公告)日:2013-05-21

    申请号:US12166491

    申请日:2008-07-02

    IPC分类号: G06F12/00 G06F13/00 G06F13/28

    摘要: A method and processor for providing full load/store queue functionality to an unordered load/store queue for a processor with out-of-order execution. Load and store instructions are inserted in a load/store queue in execution order. Each entry in the load/store queue includes an identification corresponding to a program order. Conflict detection in such an unordered load/store queue may be performed by searching a first CAM for all addresses that are the same or overlap with the address of the load or store instruction to be executed. A further search may be performed in a second CAM to identify those entries that are associated with younger or older instructions with respect to the sequence number of the load or store instruction to be executed. The output results of the Address CAM and Age CAM are logically ANDed.

    摘要翻译: 一种方法和处理器,用于向具有无序执行的处理器的无序加载/存储队列提供满载/存储队列功能。 加载和存储指令以执行顺序插入到加载/存储队列中。 加载/存储队列中的每个条目包括与程序顺序相对应的标识。 可以通过在第一CAM中搜索与要执行的加载或存储指令相同或重叠的所有地址来执行这种无序加载/存储队列中的冲突检测。 可以在第二CAM中执行进一步的搜索以识别与要执行的加载或存储指令的序列号相关联的与较年或更旧的指令相关联的那些条目。 地址CAM和Age CAM的输出结果在逻辑上为AND。

    UNORDERED LOAD/STORE QUEUE
    2.
    发明申请
    UNORDERED LOAD/STORE QUEUE 有权
    无节奏的载入/存储队列

    公开(公告)号:US20090013135A1

    公开(公告)日:2009-01-08

    申请号:US12166491

    申请日:2008-07-02

    IPC分类号: G06F9/312 G06F12/00

    摘要: A method and processor for providing full load/store queue functionality to an unordered load/store queue for a processor with out-of-order execution. Load and store instructions are inserted in a load/store queue in execution order. Each entry in the load/store queue includes an identification corresponding to a program order. Conflict detection in such an unordered load/store queue may be performed by searching a first CAM for all addresses that are the same or overlap with the address of the load or store instruction to be executed. A further search may be performed in a second CAM to identify those entries that are associated with younger or older instructions with respect to the sequence number of the load or store instruction to be executed. The output results of the Address CAM and Age CAM are logically ANDed.

    摘要翻译: 一种方法和处理器,用于向具有无序执行的处理器的无序加载/存储队列提供满载/存储队列功能。 加载和存储指令以执行顺序插入到加载/存储队列中。 加载/存储队列中的每个条目包括与程序顺序相对应的标识。 可以通过在第一CAM中搜索与要执行的加载或存储指令相同或重叠的所有地址来执行这种无序加载/存储队列中的冲突检测。 可以在第二CAM中执行进一步的搜索以识别与要执行的加载或存储指令的序列号相关联的与较年或更旧的指令相关联的那些条目。 地址CAM和Age CAM的输出结果在逻辑上为AND。

    SCALABLE PROCESSING ARCHITECTURE
    5.
    发明申请
    SCALABLE PROCESSING ARCHITECTURE 有权
    可扩展的处理结构

    公开(公告)号:US20080244230A1

    公开(公告)日:2008-10-02

    申请号:US12136645

    申请日:2008-06-10

    IPC分类号: G06F9/30 G06F9/38

    CPC分类号: G06F15/8007 G06F9/4494

    摘要: A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes and external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.

    摘要翻译: 根据本发明的各种实施例的计算节点包括能够耦合到至少一个第一其他计算节点的至少一个输入端口,耦合到所述输入端口以存储输入数据的第一存储器,用于接收的第二存储器 并且存储指令,将输入数据与指令相匹配的指令唤醒单元,使用输入数据产生输出数据的执行指令的至少一个执行单元,以及至少能够耦合到至少一个 第二个其他计算节点。 节点还可以包括将输出数据从输出端口引导到第二另一个节点的路由器。 根据本发明的各种实施例的系统包括用于获取一组指令的外部指令定序器和一个或多个互连的预先选择的计算节点。 根据本发明的实施例的物品包括具有能够使机器将程序分成多组指令的指令的介质,将一个或多个指令组分配给多个互连的预选计算节点, 将指令组加载到节点,并执行指令组,因为每个组中的每个指令都接收所有必需的相关操作数以供执行。

    COMBINED BRANCH TARGET AND PREDICATE PREDICTION

    公开(公告)号:US20130086370A1

    公开(公告)日:2013-04-04

    申请号:US13321807

    申请日:2010-06-18

    IPC分类号: G06F9/38

    摘要: Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed.

    Computing nodes for executing groups of instructions
    7.
    发明授权
    Computing nodes for executing groups of instructions 有权
    计算用于执行指令组的节点

    公开(公告)号:US08055881B2

    公开(公告)日:2011-11-08

    申请号:US12136645

    申请日:2008-06-10

    IPC分类号: G06F15/163

    CPC分类号: G06F15/8007 G06F9/4494

    摘要: A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes and external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.

    摘要翻译: 根据本发明的各种实施例的计算节点包括能够耦合到至少一个第一其他计算节点的至少一个输入端口,耦合到所述输入端口以存储输入数据的第一存储器,用于接收的第二存储器 并且存储指令,将输入数据与指令相匹配的指令唤醒单元,使用输入数据产生输出数据的执行指令的至少一个执行单元,以及至少能够耦合到至少一个 第二个其他计算节点。 节点还可以包括将输出数据从输出端口引导到第二另一个节点的路由器。 根据本发明的各种实施例的系统包括用于获取一组指令的外部指令定序器和一个或多个互连的预先选择的计算节点。 根据本发明的实施例的物品包括具有能够使机器将程序分成多组指令的指令的介质,将一个或多个指令组分配给多个互连的预选计算节点, 将指令组加载到节点,并执行指令组,因为每个组中的每个指令都接收所有必需的相关操作数以供执行。

    Combined branch target and predicate prediction for instruction blocks
    8.
    发明授权
    Combined branch target and predicate prediction for instruction blocks 有权
    组合分支目标和指令块的谓词预测

    公开(公告)号:US09021241B2

    公开(公告)日:2015-04-28

    申请号:US13321807

    申请日:2010-06-18

    IPC分类号: G06F9/38 G06F9/455

    摘要: Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed.

    摘要翻译: 实施例提供了在使用组合分支目标和谓词预测的程序执行期间与预测谓词和分支目标相关联的方法,装置,系统和计算机可读介质。 可以使用表示程序中的指令块中的谓词和块之间的分支的一个或多个预测控制流程图来进行预测。 预测控制流图可以被构造为树,使得图中的每个节点与谓词指令相关联,并且每个叶与跳转到另一块的分支目标相关联。 在块的执行期间,预测发生器可以采取控制点历史并产生预测。 按照通过树的预测建议的路径,可以预测谓词值和分支目标。 可以描述和要求保护其他实施例。