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    ERROR CORRECTING POINTERS FOR NON-VOLATILE STORAGE
    4.
    发明申请
    ERROR CORRECTING POINTERS FOR NON-VOLATILE STORAGE 有权
    用于非易失存储器的错误修正指针

    公开(公告)号：US20110296258A1

    公开(公告)日：2011-12-01

    申请号：US12788329

    申请日：2010-05-27

    申请人： Stuart Schechter ,  Karin Strauss ,  Gabriel Loh ,  Douglas C. Burger

    发明人： Stuart Schechter ,  Karin Strauss ,  Gabriel Loh ,  Douglas C. Burger

    IPC分类号： H03M13/05 ,  G06F11/00 ,  G06F11/10

    CPC分类号： G06F11/1048 ,  G11C13/0004 ,  H03M13/09 ,  H03M13/19

    摘要： Architecture that implements error correcting pointers (ECPs) with a memory row, which point to the address of failed memory cells, each of which is paired with a replacement cell to be substituted for the failed cell. If two error correcting pointers in the array point to the same cell, a precedence rule dictates the array entry with the higher index (the entry created later) takes precedence. To count the number of error correcting pointers in use, a null pointer address can be employed to indicate that a pointer is inactive, an activation bit can be added, and/or a counter, that represents the number of error correcting pointers that are active. Mechanisms are provided for wear-leveling within the error correction structure, or for pairing this scheme with single-error correcting bits for instances where transient failures may occur. The architecture also employs pointers to correct errors in volatile and non-volatile memories.

    摘要翻译： 使用存储器行实现错误校正指针（ECP）的架构，其指向故障存储器单元的地址，每个存储器单元与替换单元配对以替代故障单元。 如果数组中的两个纠错指针指向同一个单元格，则优先级规则将指定具有较高索引的数组条目（稍后创建的条目）优先。 为了对正在使用的纠错指针的数量进行计数，可以采用空指针地址来指示指针不活动，可以添加激活位，和/或计数器，其表示有效的纠错指针的数目 。 提供了用于纠错结构内的磨损均衡的机制，或者用于将该方案与用于可能发生瞬态故障的情况的单错误校正位配对。 该架构还使用指针来纠正易失性和非易失性存储器中的错误。

    SCALABLE PROCESSING ARCHITECTURE
    5.
    发明申请
    SCALABLE PROCESSING ARCHITECTURE 有权
    可扩展的处理结构

    公开(公告)号：US20080244230A1

    公开(公告)日：2008-10-02

    申请号：US12136645

    申请日：2008-06-10

    申请人： Douglas C. Burger ,  Stephen W. Keckler ,  Karthikevan Sankaralingam ,  Ramadass Nagarajan

    发明人： Douglas C. Burger ,  Stephen W. Keckler ,  Karthikevan Sankaralingam ,  Ramadass Nagarajan

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F15/8007 ,  G06F9/4494

    摘要： A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes and external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.

    摘要翻译： 根据本发明的各种实施例的计算节点包括能够耦合到至少一个第一其他计算节点的至少一个输入端口，耦合到所述输入端口以存储输入数据的第一存储器，用于接收的第二存储器 并且存储指令，将输入数据与指令相匹配的指令唤醒单元，使用输入数据产生输出数据的执行指令的至少一个执行单元，以及至少能够耦合到至少一个 第二个其他计算节点。 节点还可以包括将输出数据从输出端口引导到第二另一个节点的路由器。 根据本发明的各种实施例的系统包括用于获取一组指令的外部指令定序器和一个或多个互连的预先选择的计算节点。 根据本发明的实施例的物品包括具有能够使机器将程序分成多组指令的指令的介质，将一个或多个指令组分配给多个互连的预选计算节点， 将指令组加载到节点，并执行指令组，因为每个组中的每个指令都接收所有必需的相关操作数以供执行。