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11 条记录 (耗时 0.035 秒)

    Plasma in-situ treatment of chemically amplified resist
    4.
    发明授权
    Plasma in-situ treatment of chemically amplified resist 有权
    化学放大抗蚀剂的等离子体原位处理

    公开(公告)号：US07347915B1

    公开(公告)日：2008-03-25

    申请号：US11326934

    申请日：2006-01-05

    申请人： Douglas L. Keil ,  Wan-Lin Chen ,  Eric A. Hudson ,  S. M. Reza Sadjadi ,  Mark H. Wilcoxson ,  Andrew D. Bailey, III

    发明人： Douglas L. Keil ,  Wan-Lin Chen ,  Eric A. Hudson ,  S. M. Reza Sadjadi ,  Mark H. Wilcoxson ,  Andrew D. Bailey, III

    IPC分类号： H01L21/00

    CPC分类号： H01L21/0273

    摘要： A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.

    摘要翻译： 提供了通过在晶片上蚀刻层来制造半导体器件的方法。 在晶片上设置光致抗蚀剂层。 对光致抗蚀剂层进行图案化。 将晶片放置在处理室中。 通过在处理室中提供含有高能电子的硬化等离子体使光致抗蚀剂硬化，使光致抗蚀剂层硬化，其中高能电子具有密度。 该层在处理室内用蚀刻等离子体蚀刻，其中蚀刻等离子体中高能电子的密度小于硬化等离子体中高能电子的密度。

    Plasma in-situ treatment of chemically amplified resist
    5.
    发明授权
    Plasma in-situ treatment of chemically amplified resist 有权
    化学放大抗蚀剂的等离子体原位处理

    公开(公告)号：US07022611B1

    公开(公告)日：2006-04-04

    申请号：US10426043

    申请日：2003-04-28

    申请人： Douglas L. Keil ,  Wan-Lin Chen ,  Eric A. Hudson ,  S. M. Reza Sadjadi ,  Mark H. Wilcoxson ,  Andrew D. Bailey, III

    发明人： Douglas L. Keil ,  Wan-Lin Chen ,  Eric A. Hudson ,  S. M. Reza Sadjadi ,  Mark H. Wilcoxson ,  Andrew D. Bailey, III

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0273

    摘要： A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.

    摘要翻译： 提供了通过在晶片上蚀刻层来制造半导体器件的方法。 在晶片上设置光致抗蚀剂层。 对光致抗蚀剂层进行图案化。 将晶片放置在处理室中。 通过在处理室中提供含有高能电子的硬化等离子体使光致抗蚀剂硬化，使光致抗蚀剂层硬化，其中高能电子具有密度。 该层在处理室内用蚀刻等离子体蚀刻，其中蚀刻等离子体中高能电子的密度小于硬化等离子体中高能电子的密度。

    Capacitively-coupled electrostatic (CCE) probe arrangement for detecting dechucking in a plasma processing chamber and methods thereof
    6.
    发明授权
    Capacitively-coupled electrostatic (CCE) probe arrangement for detecting dechucking in a plasma processing chamber and methods thereof 有权
    用于检测等离子体处理室中的脱扣的电容耦合静电（CCE）探针装置及其方法

    公开(公告)号：US08780522B2

    公开(公告)日：2014-07-15

    申请号：US12498939

    申请日：2009-07-07

    申请人： Jean-Paul Booth ,  Douglas L. Keil

    发明人： Jean-Paul Booth ,  Douglas L. Keil

    IPC分类号： H01L21/683

    CPC分类号： H01L21/6833

    摘要： A method for identifying a signal perturbation characteristic of a dechucking event within a processing chamber of a plasma processing system is provided. The method includes executing a dechucking step within the processing chamber to remove a substrate from a lower electrode, wherein the dechucking step includes generating plasma capable of providing a current to neutralize an electrostatic charge on the substrate. The method also includes employing a probe head to collect a set of characteristic parameter measurements during the dechucking step. The probe head is on a surface of the processing chamber, wherein the surface is within close proximity to a substrate surface. The method further includes comparing the set of characteristic parameter measurements against a pre-defined range. If the set of characteristic parameter measurements is within the pre-defined range, the electrostatic charge is removed from the substrate and the signal perturbation characteristic of the dechucking event is detected.

    摘要翻译： 提供了一种用于识别等离子体处理系统的处理室内的消磁事件的信号扰动特性的方法。 该方法包括执行处理室内的脱扣步骤以从下电极去除衬底，其中所述去开关步骤包括产生能够提供电流以中和衬底上的静电电荷的等离子体。 该方法还包括使用探针头在脱胶步骤期间收集一组特征参数测量。 探头位于处理室的表面上，其中表面在基板表面附近。 该方法还包括将特征参数测量集合与预定义范围进行比较。 如果特征参数测量集合在预定范围内，则从衬底去除静电电荷，并且检测到脱扣事件的信号扰动特性。

    CAPACITIVELY-COUPLED ELECTROSTATIC (CCE) PROBE ARRANGEMENT FOR DETECTING DECHUCKING IN A PLASMA PROCESSING CHAMBER AND METHODS THEREOF
    7.
    发明申请
    CAPACITIVELY-COUPLED ELECTROSTATIC (CCE) PROBE ARRANGEMENT FOR DETECTING DECHUCKING IN A PLASMA PROCESSING CHAMBER AND METHODS THEREOF 有权
    用于检测等离子体加工室中的检测的电容耦合静电（CCE）检测装置及其方法

    公开(公告)号：US20100008015A1

    公开(公告)日：2010-01-14

    申请号：US12498939

    申请日：2009-07-07

    申请人： Jean-Paul Booth ,  Douglas L. Keil

    发明人： Jean-Paul Booth ,  Douglas L. Keil

    IPC分类号： H01L21/683

    CPC分类号： H01L21/6833

    摘要： A method for identifying a signal perturbation characteristic of a dechucking event within a processing chamber of a plasma processing system is provided. The method includes executing a dechucking step within the processing chamber to remove a substrate from a lower electrode, wherein the dechucking step includes generating plasma capable of providing a current to neutralize an electrostatic charge on the substrate. The method also includes employing a probe head to collect a set of characteristic parameter measurements during the dechucking step. The probe head is on a surface of the processing chamber, wherein the surface is within close proximity to a substrate surface. The method further includes comparing the set of characteristic parameter measurements against a pre-defined range. If the set of characteristic parameter measurements is within the pre-defined range, the electrostatic charge is removed from the substrate and the signal perturbation characteristic of the dechucking event is detected.

    摘要翻译： 提供了一种用于识别等离子体处理系统的处理室内的消磁事件的信号扰动特性的方法。 该方法包括执行处理室内的脱扣步骤以从下电极去除衬底，其中所述去开关步骤包括产生能够提供电流以中和衬底上的静电电荷的等离子体。 该方法还包括使用探针头在脱胶步骤期间收集一组特征参数测量。 探头位于处理室的表面上，其中表面在基板表面附近。 该方法还包括将特征参数测量集合与预定义范围进行比较。 如果特征参数测量集合在预定范围内，则从衬底去除静电电荷，并且检测到脱扣事件的信号扰动特性。

    CAPACITIVELY-COUPLED ELECTROSTATIC (CCE) PROBE ARRANGEMENT FOR DETECTING STRIKE STEP IN A PLASMA PROCESSING CHAMBER AND METHODS THEREOF
    8.
    发明申请
    CAPACITIVELY-COUPLED ELECTROSTATIC (CCE) PROBE ARRANGEMENT FOR DETECTING STRIKE STEP IN A PLASMA PROCESSING CHAMBER AND METHODS THEREOF 有权
    用于检测等离子体加工室中的冲击步骤的电容耦合静电（CCE）探测器布置及其方法

    公开(公告)号：US20100006417A1

    公开(公告)日：2010-01-14

    申请号：US12498936

    申请日：2009-07-07

    申请人： Jean-Paul Booth ,  Douglas L. Keil

    发明人： Jean-Paul Booth ,  Douglas L. Keil

    IPC分类号： H05H1/24 ,  B01J19/08

    CPC分类号： H05H1/0081 ,  H05H1/0012

    摘要： A method for identifying a stabilized plasma within a processing chamber of a plasma processing system is provided. The method includes executing a strike step within the processing chamber to generate a plasma. The strike step includes applying a substantially high gas pressure within the processing chamber and maintaining a low radio frequency (RF) power within the processing chamber. The method also includes employing a probe head to collect a set of characteristic parameter measurements during the strike step, the probe head being on a surface of the processing chamber, wherein the surface is within close proximity to a substrate surface. The method further includes comparing the set of characteristic parameter measurements against a pre-defined range. If the set of characteristic parameter measurements is within the pre-defined range, the stabilized plasma exists.

    摘要翻译： 提供了一种在等离子体处理系统的处理室内识别稳定的等离子体的方法。 该方法包括在处理室内执行击打步骤以产生等离子体。 冲击步骤包括在处理室内施加基本上高的气体压力并且在处理室内保持低射频（RF）功率。 该方法还包括采用探针头在罢工步骤期间收集一组特征参数测量值，探针头位于处理室的表面上，其中该表面紧邻衬底表面。 该方法还包括将特征参数测量集合与预定义范围进行比较。 如果一组特征参数测量值在预定范围内，则存在稳定的等离子体。

    Controlling plasma processing using parameters derived through the use of a planar ion flux probing arrangement
    9.
    发明授权
    Controlling plasma processing using parameters derived through the use of a planar ion flux probing arrangement 有权
    使用通过使用平面离子通量探测装置得到的参数来控制等离子体处理

    公开(公告)号：US07413672B1

    公开(公告)日：2008-08-19

    申请号：US11398306

    申请日：2006-04-04

    申请人： Douglas L. Keil

    发明人： Douglas L. Keil

    IPC分类号： G01L21/30 ,  G01R31/00

    CPC分类号： H01J37/32935 ,  G01R19/0061 ,  H01J37/32954 ,  H01J37/3299

    摘要： Methods and apparatus for detecting and/or deriving the absolute values of and/or the relative changes in parameters such as the plasma potential and the ion flux using a Planar Ion Flux (PIF) probing arrangement are disclosed. The detected and/or derived values are then employed to control plasma processing processes.

    摘要翻译： 公开了使用平面离子通量（PIF）探测装置来检测和/或导出诸如等离子体电位和离子通量的参数的绝对值和/或相对变化的方法和装置。 然后使用检测到的和/或导出的值来控制等离子体处理过程。

    Methods of forming memory cell capacitor plates in memory cell capacitor structures
    10.
    发明授权
    Methods of forming memory cell capacitor plates in memory cell capacitor structures 有权
    在存储单元电容器结构中形成存储单元电容器板的方法

    公开(公告)号：US06268260B1

    公开(公告)日：2001-07-31

    申请号：US09281866

    申请日：1999-03-31

    申请人： Douglas L. Keil

    发明人： Douglas L. Keil

    IPC分类号： H01L2120

    CPC分类号： H01L28/60 ,  H01L21/76885 ,  H01L28/55

    摘要： An improved method of forming a memory cell capacitor plate is disclosed. The method of forming a memory cell capacitor plate comprises the steps of depositing a sacrificial layer and forming an opening in the sacrificial layer. Then an electrode material layer which includes a substantially conductive material that remains substantially conductive upon exposure to oxygen is deposited over a top surface of the sacrificial layer and at least partially filling the opening. The method continues with removing a portion of the electrode material layer down to at least about a level of the sacrificial layer's top surface to define a top surface of the memory cell capacitor plate, followed by removal of the sacrificial layer.

    摘要翻译： 公开了一种形成存储单元电容器板的改进方法。 形成存储单元电容器板的方法包括沉积牺牲层并在牺牲层中形成开口的步骤。 然后，包括基本上导电的材料的电极材料层，其在暴露于氧气时保持基本导电，沉积在牺牲层的顶表面上并且至少部分地填充开口。 该方法继续将电极材料层的一部分下降至至少约牺牲层顶表面的水平以限定存储单元电容器板的顶表面，随后移除牺牲层。