公开(公告)号：US06677775B2

公开(公告)日：2004-01-13

申请号：US09757746

申请日：2001-01-10

申请人： Douglas W. Babcock

发明人： Douglas W. Babcock

IPC分类号： G01R3128

CPC分类号： G01R31/31924 ,  G01R31/31926

摘要： A circuit testing apparatus includes a controlling processor for controlling stimulus signals to be applied to a circuit under test and for processing and storing response signals generated by the circuit under test in response to the stimulus signals. The stimulus signals are generated by a driver portion of a receiver/driver circuit coupled to a pin on the circuit under test. The driver includes an output stage circuit coupled to the pin on the circuit under test. The output stage circuit includes a linear amplifier circuit which receives a control signal via the controlling processor and generates from the control signal a drive signal to be applied to the circuit under test. The linear amplifier allows the driver to produce a drive signal with a high level of voltage and timing accuracy and, in the case of digital square pulse signals, a high level of pulse symmetry.

摘要翻译： 电路测试装置包括控制处理器，用于控制要施加到被测电路的刺激信号，并且响应于刺激信号来处理和存储由被测电路产生的响应信号。 激励信号由耦合到被测电路上的引脚的接收器/驱动器电路的驱动器部分产生。 驱动器包括耦合到被测电路上的引脚的输出级电路。 输出级电路包括线性放大器电路，其经由控制处理器接收控制信号，并从控制信号产生要施加到被测电路的驱动信号。 线性放大器允许驱动器产生具有高电平和定时精度的驱动信号，并且在数字方波脉冲信号的情况下具有高水平的脉冲对称性。

公开(公告)号：US5010297A

公开(公告)日：1991-04-23

申请号：US444815

申请日：1989-12-01

申请人： Douglas W. Babcock

发明人： Douglas W. Babcock

IPC分类号： G01R31/28 ,  G01R31/319

CPC分类号： G01R31/31924 ,  G01R31/2851

摘要： Automatic test equipment (ATE) for post-production testing of multi-pin integrated circuits (ICs). Each pin is assigned to a pin card having a pin driver and an active load with the latter including both a current source and a current sink. The pin driver and active load are connectable alternatively to the IC pin in response to complementary inhibit signals. Within the active load, the source and sink and connected/disconnected by respective pairs of matched transistor switch circuits the individual switches of which are alternatively activatable by differential control means. Both switch circuits of each pair are supplied from a single current source. One switch circuit of each pair, when activated, directs the current from the single current source to (from) the IC pin, while the other switch circuit, when activated, directs the current to (from) a return line. All of the switch circuits include Darligton-connected transistors and an additional transistor to draw base charge from the principal Darlington transistor when the switch is turned off.

摘要翻译： 自动测试设备（ATE）用于多针集成电路（IC）的后期制作测试。 每个引脚分配给具有引脚驱动器和有源负载的引脚卡，后者包括电流源和电流接收器。 引脚驱动器和有源负载可以互补地连接到IC引脚，以响应互补的禁止信号。 在有源负载中，源极和漏极并且由相应的匹配晶体管开关电路对连接/断开，其各个开关可由差分控制装置激活。 每对的两个开关电路都由单个电流源提供。 每对的一个开关电路在被激活时将来自单个电流源的电流引导到（从）IC引脚，而另一个开关电路在被激活时将电流引导到（从）返回线。 所有的开关电路都包括达赖顿连接的晶体管和另一个晶体管，当开关断开时，从主达林顿晶体管中抽取基极电荷。

公开(公告)号：US06737857B2

公开(公告)日：2004-05-18

申请号：US10044501

申请日：2002-01-10

申请人： Douglas W. Babcock

发明人： Douglas W. Babcock

IPC分类号： G01R3128

CPC分类号： G01R31/31924 ,  G01R31/31926

摘要： A circuit testing apparatus for testing a circuit under test. The circuit testing apparatus includes a controller for controlling signals being transferred between a circuit under test and the circuit testing apparatus. The circuit testing apparatus further includes a driver circuit for generating signals to be applied to the circuit under test. The driver includes a high speed slave chain and DC control loop chain coupled to the circuit under test. The high speed slave chain receives a differential voltage logic pulse train and converts the logic pulse train into a high speed current steering for producing the drive signal to be applied to the circuit under test. The DC control loop chain provides feedback paths for DC regulation of inputs of the high speed slave chain.

摘要翻译： 一种用于测试被测电路的电路测试装置。 电路测试装置包括控制器，用于控制被测电路和电路测试装置之间传输的信号。 电路测试装置还包括用于产生要施加到被测电路的信号的驱动电路。 驱动器包括耦合到被测电路的高速从链和DC控制环链。 高速从属链接收差分电压逻辑脉冲串，并将逻辑脉冲串转换成高速电流转向，以产生要施加到被测电路的驱动信号。 DC控制回路链提供用于高速从属链输入的直流调节的反馈路径。

公开(公告)号：US5424510A

公开(公告)日：1995-06-13

申请号：US113397

申请日：1993-08-27

申请人： Alex Gusinov ,  A. Paul Brokaw ,  Douglas W. Babcock ,  Lewis Counts ,  Lawrence DeVito ,  Robert A. Duris ,  Scott Wurcer

发明人： Alex Gusinov ,  A. Paul Brokaw ,  Douglas W. Babcock ,  Lewis Counts ,  Lawrence DeVito ,  Robert A. Duris ,  Scott Wurcer

IPC分类号： H01L27/082 ,  H05B3/02

CPC分类号： H01L27/0823

摘要： A circuit for varying the temperature of a first bipolar transistor in order to thermally compensate for self-heating effects of an associated device in a common signal path with the first transistor, the first transistor being configured within an isolated collector region. The circuit includes a second bipolar transistor provided within the isolated collector region and thermally coupled to the first transistor, the second transistor operable for providing heat to the first transistor to alter the temperature to a predetermined level, thus changing the operational voltage characteristics of the first transistor so as to minimize shifts in offset voltage.

摘要翻译： 一种用于改变第一双极晶体管的温度以便热补偿与第一晶体管在公共信号路径中的相关器件的自发热效应的电路，所述第一晶体管配置在隔离的集电极区域内。 该电路包括设置在隔离的集电极区域内并热耦合到第一晶体管的第二双极晶体管，第二晶体管可操作用于向第一晶体管提供热量以将温度改变到预定电平，从而改变第一晶体管的工作电压特性 晶体管，以最小化偏移电压的偏移。

公开(公告)号：US07470968B2

公开(公告)日：2008-12-30

申请号：US11325882

申请日：2006-01-04

申请人： Douglas W. Babcock ,  Robert A. Duris ,  Bruce Hecht

发明人： Douglas W. Babcock ,  Robert A. Duris ,  Bruce Hecht

IPC分类号： H01L27/08

CPC分类号： G01R31/31924 ,  G01R31/31926

摘要： A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.

摘要翻译： 无源匹配网络连接到用于自动测试设备驱动信道的输入/输出线，以补偿与连接到该线路的接收器电路相关联的电容，以及可选的电流模式驱动器电路。 匹配电路优选地包括可以包括桥接电容器的T型线圈电路; 可以提供单独的T型线圈电路以分别补偿接收器电路和电流模式驱动电路电容。 驱动器和接收器电路可以在集成电路的公共层上实现，其中T形线圈绕组实现在与公共层与至少一个电介质层间隔开的相同集成电路的单独层中。

公开(公告)号：US07248035B2

公开(公告)日：2007-07-24

申请号：US10722970

申请日：2003-11-25

申请人： Douglas W. Babcock ,  Robert A. Duris ,  Bruce Hecht

发明人： Douglas W. Babcock ,  Robert A. Duris ,  Bruce Hecht

IPC分类号： G01R27/26

CPC分类号： G01R31/31924 ,  G01R31/31926

摘要： A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.

摘要翻译： 无源匹配网络连接到用于自动测试设备驱动信道的输入/输出线，以补偿与连接到该线路的接收器电路相关联的电容，以及可选的电流模式驱动器电路。 匹配电路优选地包括可以包括桥接电容器的T型线圈电路; 可以提供单独的T型线圈电路以分别补偿接收器电路和电流模式驱动电路电容。 驱动器和接收器电路可以在集成电路的公共层上实现，其中T形线圈绕组实现在与公共层与至少一个电介质层间隔开的相同集成电路的单独层中。

公开(公告)号：US5434446A

公开(公告)日：1995-07-18

申请号：US287478

申请日：1994-08-08

申请人： Edward B. Hilton ,  Robert A. Duris ,  Douglas W. Babcock

发明人： Edward B. Hilton ,  Robert A. Duris ,  Douglas W. Babcock

IPC分类号： H01L27/12 ,  H01L27/02

CPC分类号： H01L27/1203

摘要： A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.

摘要翻译： 用于直接键合绝缘体上硅的集成电路的寄生电容消除电路包括一个或多个制造在绝缘体上的晶体管; 晶体管外部的硅衬底区域具有要消除的寄生电容; 连接到所述晶体管外部的区域的自举端子; 以及响应于晶体管的输出并且其输出连接到自举端子的单位增益缓冲器，用于向跟随在寄生电容上产生的电压的晶体管之外的区域提供电压，并且使寄生 电容。