公开(公告)号：US08326152B2

公开(公告)日：2012-12-04

申请号：US12760870

申请日：2010-04-15

申请人： Doutje T. Van Veen ,  Adriaan J. De Lind Van Wijngaarden ,  Dusan Suvakovic

发明人： Doutje T. Van Veen ,  Adriaan J. De Lind Van Wijngaarden ,  Dusan Suvakovic

IPC分类号： H04B10/00 ,  H04B10/08 ,  H04J14/00 ,  H04J14/02

CPC分类号： H04J14/02 ,  H04B10/07955 ,  H04J3/1694

摘要： A signal strength corresponding to an incoming optical burst from each of a plurality of optical nodes is measured. The measurements can be performed at system start-up, configuration/installation of the optical nodes and/or at certain intervals of operation of the optical nodes. Signal strength information for the optical nodes based on the measurements is stored in memory. When scheduling the optical nodes for transmission, a preferred transmission order is determined in response to the stored signal strength information. In an embodiment, the preferred order is determined to reduce differences in signal strength levels between consecutive optical bursts.

摘要翻译： 测量与来自多个光学节点中的每一个的输入光脉冲串对应的信号强度。 可以在系统启动，光节点的配置/安装和/或在光节点的特定操作间隔期间进行测量。 基于测量的光节点的信号强度信息被存储在存储器中。 当调度用于传输的光节点时，响应于所存储的信号强度信息来确定优选传输顺序。 在一个实施例中，确定优选顺序以减少连续的光脉冲串之间的信号强度电平的差异。

公开(公告)号：US09996499B2

公开(公告)日：2018-06-12

申请号：US13248869

申请日：2011-09-29

申请人： Dusan Suvakovic ,  Adriaan J. de Lind van Wijngaarden ,  Man Fai Lau

发明人： Dusan Suvakovic ,  Adriaan J. de Lind van Wijngaarden ,  Man Fai Lau

IPC分类号： G06F15/78 ,  G06F9/38

CPC分类号： G06F15/7867 ,  G06F9/3897 ,  Y02D10/12 ,  Y02D10/13

摘要： A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.

公开(公告)号：US20120079236A1

公开(公告)日：2012-03-29

申请号：US13248869

申请日：2011-09-29

申请人： Dusan Suvakovic ,  Adriaan J. de Lind van Wijngaarden ,  Man Fai Lau

发明人： Dusan Suvakovic ,  Adriaan J. de Lind van Wijngaarden ,  Man Fai Lau

IPC分类号： G06F9/312 ,  G06F15/76

CPC分类号： G06F15/7867 ,  G06F9/3897 ,  Y02D10/12 ,  Y02D10/13

摘要： A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.

摘要翻译： 处理器包括多个处理器单元，其被布置为并行地并且彼此协作地操作，以及控制逻辑，其被配置为指导处理器单元的操作。 至少一个处理器单元中的一个包括存储器，算术引擎和交换结构。 交换结构提供了存储器，算术引擎和给定处理器单元的输入和输出端口之间的可控连接，并具有由控制逻辑的相应输出驱动的控制输入。 在说明性实施例中，处理器单元可以被配置为执行与里德 - 所罗门（RS）解码器或其他类型的前向纠错（FEC）解码器中的密钥方程解算器相关联的计算。

公开(公告)号：US20160268003A1

公开(公告)日：2016-09-15

申请号：US14871269

申请日：2015-09-30

申请人： Dusan Suvakovic ,  Adriaan J. de Lind Van Wijngaarden

发明人： Dusan Suvakovic ,  Adriaan J. de Lind Van Wijngaarden

IPC分类号： G11C19/00 ,  G11C7/10 ,  H04L12/935

CPC分类号： H04L49/30 ,  H04L49/1515

摘要： A network node (bridge, switch, router) and method for traffic interconnection in a communication network. The node includes an interconnection network or switch fabric having ingress and egress ports in communication with the input and output ports of the node. The interconnection network also includes an interconnector having a retiming module, a permutation module, and a re-alignment module. Data arriving at the node input ports is provided to the ingress queues of the interconnection network where it is queued, if necessary, and then processed through the interconnector so that it can be provided to an appropriate egress port. Data at the egress ports is then provided to output ports for transmission toward its intended destination.

摘要翻译： 网络节点（桥，交换机，路由器）和通信网络中流量互连的方法。 节点包括具有与节点的输入和输出端口通信的入口和出口端口的互连网络或交换结构。 互连网络还包括具有重定时模块，置换模块和重新对准模块的互连器。 到达节点输入端口的数据被提供给互连网络的进入队列，如果需要，它被排队，然后通过互连器进行处理，以便可以将其提供给适当的出口端口。 然后将出口端口的数据提供给输出端口，以朝向其预定目的地传输。

公开(公告)号：US09459927B2

公开(公告)日：2016-10-04

申请号：US12125315

申请日：2008-05-22

申请人： Martin D. Carroll ,  Hungkei Keith Chow ,  Ilija Hadzic ,  Ronald L. Sharp ,  Theodore Sizer, II ,  Dusan Suvakovic ,  Doutje T. Van Veen

发明人： Martin D. Carroll ,  Hungkei Keith Chow ,  Ilija Hadzic ,  Ronald L. Sharp ,  Theodore Sizer, II ,  Dusan Suvakovic ,  Doutje T. Van Veen

IPC分类号： G06F9/455 ,  G06F9/50 ,  G06F9/48

CPC分类号： G06F9/5077 ,  G06F9/4856

摘要： A virtual personal computer is implemented in a communication system comprising a plurality of central offices each of which communicates with a plurality of client devices over a corresponding access network. A given one of the central offices comprises at least one compute server and at least one storage server. The virtual personal computer is configured by allocating physical processing resources of the compute server and physical storage resources of the storage server to that virtual personal computer. User access is provided to the virtual personal computer via one of the client devices. The virtual personal computer can be dynamically reconfigured by altering the allocation of at least one of the physical processing resources and the physical storage resources to the given virtual personal computer responsive to particular applications selected by the user to run on the given virtual personal computer.

摘要翻译： 在包括多个中心局的通信系统中实现虚拟个人计算机，每个中心局通过相应的接入网络与多个客户端设备进行通信。 给定的一个中心局包括至少一个计算服务器和至少一个存储服务器。 通过将计算服务器的物理处理资源和存储服务器的物理存储资源分配给该虚拟个人计算机来配置虚拟个人计算机。 用户访问通过其中一个客户端设备提供给虚拟个人计算机。 响应于用户选择的在给定的虚拟个人计算机上运行的特定应用，可以通过将物理处理资源和物理存储资源中的至少一个的分配改变到给定的虚拟个人计算机来动态地重新配置虚拟个人计算机。

公开(公告)号：US20140126919A1

公开(公告)日：2014-05-08

申请号：US13853754

申请日：2013-03-29

申请人： Nagaraj Prasanth Anthapadmanabhan ,  Dusan Suvakovic ,  Hungkei Keith Chow ,  Doutje T. Van Veen

发明人： Nagaraj Prasanth Anthapadmanabhan ,  Dusan Suvakovic ,  Hungkei Keith Chow ,  Doutje T. Van Veen

IPC分类号： H04B10/66

CPC分类号： H04L25/03866 ,  H04L1/0071

摘要： A manner of processing bit-interleaved data traffic in a communication network. In the increasingly-common scenario where data traffic is bit interleaved and scrambled using a PRBS (pseudo-random binary sequence) before it is transmitted from a sender to a receiver, the receiver is configured to receive the transmitted bit stream and decimate it, that is, remove the bits of the bit stream that are allocated for the receiver, prior to descrambling. To accomplish this, the receiver employs an LFSR (linear feedback shift register) similar or identical to the one used by the sender to scramble the data. The LFSR is initialized by employing helper bits inserted by the sender or an initialization unit, and may employ other techniques for phase adjustment or state skipping depending on the nature of the transmitted bit stream.

摘要翻译： 在通信网络中处理比特交织的数据业务的方式。 在越来越常见的情况下，在从发送器发送到接收器之前，使用PRBS（伪随机二进制序列）将数据业务进行比特交织和加扰，接收器被配置为接收所发送的比特流并对其进行抽取， 是在解扰之前去除分配给接收机的比特流的比特。 为了实现这一点，接收机采用与发送方使用的LFSR（线性反馈移位寄存器）类似或相同的数据来加扰数据。 通过使用由发送者或初始化单元插入的辅助位来初始化LFSR，并且可以根据发送的比特流的性质使用用于相位调整或状态跳过的其他技术。

公开(公告)号：US07242739B2

公开(公告)日：2007-07-10

申请号：US10460572

申请日：2003-06-12

申请人： Glenn M Boles ,  Alfred Earl Dunlop ,  Manyalibo Joseph Matthews ,  Dusan Suvakovic ,  Doutje T. Van Veen

发明人： Glenn M Boles ,  Alfred Earl Dunlop ,  Manyalibo Joseph Matthews ,  Dusan Suvakovic ,  Doutje T. Van Veen

IPC分类号： H03D3/24

CPC分类号： H04L7/0338 ,  H04L7/042

摘要： A method and apparatus for clock and data recovery that is advantageous in burst-mode systems is disclosed. This clock and data recovery method allows a) fast locking to a rapidly changed phase of the transmission clock, and b) stable tracking of a slowly changing phase of the transmission clock. Such fast locking minimizes the “guard band” between consecutive transmission bursts, while stable tracking provides reliable data tracking, resulting in the efficient use of bandwidth. A plurality of clock signals, is generated, each having a different phase. The phase of an input signal data stream is determined and a desired clock signal in the plurality that corresponds to the phase of the input data stream is selected and used to sample the input signal data stream.

摘要翻译： 公开了一种在突发模式系统中有利的用于时钟和数据恢复的方法和装置。 该时钟和数据恢复方法允许a）快速锁定到传输时钟的快速变化的相位，以及b）稳定跟踪传输时钟的缓慢变化的相位。 这种快速锁定使连续传输突发之间的“保护带”最小化，而稳定跟踪提供可靠的数据跟踪，导致带宽的有效使用。 产生多个时钟信号，每个具有不同的相位。 确定输入信号数据流的相位，并且选择与输入数据流的相位相对应的多个中的期望时钟信号，并将其用于采样输入信号数据流。

公开(公告)号：US09729360B2

公开(公告)日：2017-08-08

申请号：US13853754

申请日：2013-03-29

申请人： Nagaraj Prasanth Anthapadmanabhan ,  Dusan Suvakovic ,  Hungkei Keith Chow ,  Doutje T. Van Veen

发明人： Nagaraj Prasanth Anthapadmanabhan ,  Dusan Suvakovic ,  Hungkei Keith Chow ,  Doutje T. Van Veen

IPC分类号： H04L25/03 ,  H04L1/00

CPC分类号： H04L25/03866 ,  H04L1/0071

摘要： A manner of processing bit-interleaved data traffic in a communication network. In the increasingly-common scenario where data traffic is bit interleaved and scrambled using a PRBS (pseudo-random binary sequence) before it is transmitted from a sender to a receiver, the receiver is configured to receive the transmitted bit stream and decimate it, that is, remove the bits of the bit stream that are allocated for the receiver, prior to descrambling. To accomplish this, the receiver employs an LFSR (linear feedback shift register) similar or identical to the one used by the sender to scramble the data. The LFSR is initialized by employing helper bits inserted by the sender or an initialization unit, and may employ other techniques for phase adjustment or state skipping depending on the nature of the transmitted bit stream.

公开(公告)号：US20090293055A1

公开(公告)日：2009-11-26

申请号：US12125315

申请日：2008-05-22

申请人： Martin D. Carroll ,  Hungkei Keith Chow ,  Ilija Hadzic ,  Ronald L. Sharp ,  Theodore Sizer, II ,  Dusan Suvakovic ,  Doutje T. Van Veen

发明人： Martin D. Carroll ,  Hungkei Keith Chow ,  Ilija Hadzic ,  Ronald L. Sharp ,  Theodore Sizer, II ,  Dusan Suvakovic ,  Doutje T. Van Veen

IPC分类号： G06F9/455

CPC分类号： G06F9/5077 ,  G06F9/4856

摘要： A virtual personal computer is implemented in a communication system comprising a plurality of central offices each of which communicates with a plurality of client devices over a corresponding access network. A given one of the central offices comprises at least one compute server and at least one storage server. The virtual personal computer is configured by allocating physical processing resources of the compute server and physical storage resources of the storage server to that virtual personal computer. User access is provided to the virtual personal computer via one of the client devices. The virtual personal computer can be dynamically reconfigured by altering the allocation of at least one of the physical processing resources and the physical storage resources to the given virtual personal computer responsive to particular applications selected by the user to run on the given virtual personal computer.

摘要翻译： 在包括多个中心局的通信系统中实现虚拟个人计算机，每个中心局通过相应的接入网络与多个客户端设备进行通信。 给定的一个中心局包括至少一个计算服务器和至少一个存储服务器。 通过将计算服务器的物理处理资源和存储服务器的物理存储资源分配给该虚拟个人计算机来配置虚拟个人计算机。 用户访问通过其中一个客户端设备提供给虚拟个人计算机。 响应于用户选择的在给定的虚拟个人计算机上运行的特定应用，可以通过将物理处理资源和物理存储资源中的至少一个的分配改变到给定的虚拟个人计算机来动态地重新配置虚拟个人计算机。

公开(公告)号：US07123675B2

公开(公告)日：2006-10-17

申请号：US10255008

申请日：2002-09-25

申请人： Glenn M Boles ,  Alfred Earl Dunlop ,  Ilija Hadzic ,  Manyalibo Joseph Matthews ,  Dusan Suvakovic ,  Doutje T. Van Veen

发明人： Glenn M Boles ,  Alfred Earl Dunlop ,  Ilija Hadzic ,  Manyalibo Joseph Matthews ,  Dusan Suvakovic ,  Doutje T. Van Veen

IPC分类号： H04L7/00

CPC分类号： H04J3/1694 ,  H04J3/0682 ,  H04L7/042

摘要： A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter. The phase difference between the data word and the receiver clock is determined by the offset of a word relative to a desired position in a storage buffer. The FIFO delay is determined either by measuring the difference between a read pointer and a write pointer in the FIFO or, alternatively, by calculating the difference between a timestamp of the time a data word entered the FIFO and the current time as the data word is read from the FIFO.

摘要翻译： 公开了一种时钟恢复方法，其中数据字的FIFO延迟和数据字与接收机时钟之间的相位差用于对发射机进行数据传输。 数据字和接收器时钟之间的相位差由字相对于存储缓冲器中的期望位置的偏移量确定。 通过测量FIFO中的读指针和写指针之间的差来确定FIFO延迟，或者通过计算数据字进入FIFO的时间与当前时间的时间戳之间的差， 从FIFO读取。