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1.发明申请公开(公告)号：US20180158204A1
公开(公告)日：2018-06-07
申请号：US15833518
申请日：2017-12-06
Inventor： Hyun Kyu Yu , Sung Weon Kang , Bon Tae Koo , Joo Hyun Lee
CPC classification number: G06T7/50 , H04N5/374 , H04N13/128 , H04N13/214 , H04N13/218 , H04N13/271 , H04N2213/003
Abstract: Provided is an image processing device. The device includes an active pixel sensor array including a plurality of pixels configured to generate a plurality of signals corresponding to a target, and an image processor configured to generate a depth map about the target based on an intensity difference of two signals among the plurality of signals.
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公开(公告)号：US09013216B2
公开(公告)日：2015-04-21
申请号：US14028707
申请日：2013-09-17
Inventor： Hyun Ho Boo , Byung Hun Min , Duong Quoc Hoang , Cheon Soo Kim , Hyun Kyu Yu
Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.
Abstract translation: 公开了一种数字锁相环，包括：时间数字转换器（TDC），被配置为基于输入时钟和参考时钟输出数字位，其中TDC包括：第一仲裁器组，其被配置为补偿 对于具有第一平均偏移的输入时钟和参考时钟之间的相位差，并输出第一逻辑值; 第二仲裁器组，被配置为用第二平均偏移补偿所述输入时钟和所述参考时钟之间的相位差，并输出第二逻辑值; 以及信号处理器，被配置为基于第一和第二逻辑值输出数字位。
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公开(公告)号：US11507811B2
公开(公告)日：2022-11-22
申请号：US16813901
申请日：2020-03-10
Inventor： Hyun Kyu Yu , Young-Su Kwon , Joo Hyun Lee
Abstract: An electronic device includes first to n-th cells (‘n’ is an integer of 2 or more) that receive spatial-temporal input signals that indicate an event unit in a time window, a summation circuit that sums first to n-th cell signals recorded in the first to n-th cells for each of first to m-th unit times (‘m’ is an integer of 2 or more) dividing the time window to generate first to m-th summation signals, and an encoding circuit that compares each of the first to m-th summation signals with a threshold value to encode the spatial-temporal input signals into a code of the event unit.
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4.发明授权公开(公告)号：US10929994B2
公开(公告)日：2021-02-23
申请号：US15833518
申请日：2017-12-06
Inventor： Hyun Kyu Yu , Sung Weon Kang , Bon Tae Koo , Joo Hyun Lee
IPC: G06T7/50 , H04N13/214 , H04N13/128 , H04N13/218 , H04N13/271 , H04N5/374
Abstract: Provided is an image processing device. The device includes an active pixel sensor array including a plurality of pixels configured to generate a plurality of signals corresponding to a target, and an image processor configured to generate a depth map about the target based on an intensity difference of two signals among the plurality of signals.
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5.发明申请公开(公告)号：US20140169512A1
公开(公告)日：2014-06-19
申请号：US14183513
申请日：2014-02-18
Inventor： Jung Woo PARK , Young Jae LEE , Hyun Kyu Yu , Byung Hun MIN , Seong Do KIM , Hoai Nam NGUYEN , Sang Gug LEE
IPC: H04L25/08
CPC classification number: H04L25/08 , H03D7/1441 , H03D7/1458 , H03H19/004
Abstract: A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.
Abstract translation: 直接转换接收机包括：高线性混频器装置，包括：采样单元，根据采样频率对输入电流进行采样;以及缓冲单元，其具有低输入阻抗，从采样器单元接收输出信号，放大接收信号 ，并输出电流信号; 以及滤波器装置对来自混频器装置的输出信号进行抽取，并对抽取的信号进行FIR滤波。
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Patent Agency Ranking
公开(公告)号：US20130321198A1
公开(公告)日：2013-12-05
申请号：US13759333
申请日：2013-02-05
Inventor： Pil Jae PARK , Cheon Soo Kim , Hyun Kyu Yu
IPC: G01S13/02
CPC classification number: G01S13/02 , G01S7/032 , G01S13/726 , G01S13/878 , G01S13/92
Abstract: A MIMO radar system includes one or more receivers and transmitters. Any one of the one or more transmitters provides a reference signal for injection-locking. The MIMO radar system generates multiple signals having phase and frequency which are injection-locked to those of the reference signal.
Abstract translation: MIMO雷达系统包括一个或多个接收机和发射机。 一个或多个发射器中的任何一个提供用于注射锁定的参考信号。 MIMO雷达系统产生具有相位和频率的多个信号，其被注入锁定到参考信号的信号。
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7.发明申请公开(公告)号：US20130268572A1
公开(公告)日：2013-10-10
申请号：US13854041
申请日：2013-03-29
Inventor： Seon-Ho Han , Hyun Kyu Yu
IPC: G06F17/10
CPC classification number: G06F17/10 , H03M1/0665 , H03M1/665 , H03M3/464
Abstract: Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a preset unit configured to output a preset value or a 0 value according to whether a carry of the first adder is generated; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform the add operation and input the add operation to the register and the data weighted average device including the accumulator, it is possible to improve the nonlinearity occurring in the data converter by generating a number of DAC codes in addition to 2n DAC codes.
Abstract translation: 公开了一种用于降低数据转换器的非线性的累加器和包括累加器的数据加权平均装置。 根据累加器，包括配置为根据时钟信号输出输入数据的寄存器; 第一加法器，被配置为接收具有任何位宽度的数字输入信号和来自寄存器的输出信号以执行加法运算; 预置单元，被配置为根据第一加法器的进位是否产生预置值或0值; 以及第二加法器，其被配置为接收第一加法器的输出信号和预设单元的输出信号以执行加法运算，并将加法运算输入到寄存器和包括累加器的数据加权平均装置，可以提高 通过生成除了2n个DAC代码之外的多个DAC代码，在数据转换器中发生非线性。
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公开(公告)号：US09378184B2
公开(公告)日：2016-06-28
申请号：US13854041
申请日：2013-03-29
Inventor： Seon-Ho Han , Hyun Kyu Yu
CPC classification number: G06F17/10 , H03M1/0665 , H03M1/665 , H03M3/464
Abstract: Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a preset unit configured to output a preset value or a 0 value according to whether a carry of the first adder is generated; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform the add operation and input the add operation to the register and the data weighted average device including the accumulator, it is possible to improve the nonlinearity occurring in the data converter by generating a number of DAC codes in addition to 2n DAC codes.
Abstract translation: 公开了一种用于降低数据转换器的非线性的累加器和包括累加器的数据加权平均装置。 根据累加器，包括配置为根据时钟信号输出输入数据的寄存器; 第一加法器，被配置为接收具有任何位宽度的数字输入信号和来自寄存器的输出信号以执行加法运算; 预置单元，被配置为根据第一加法器的进位是否产生预置值或0值; 以及第二加法器，其被配置为接收第一加法器的输出信号和预设单元的输出信号以执行加法运算，并将加法运算输入到寄存器和包括累加器的数据加权平均装置，可以提高 通过生成除了2n个DAC代码之外的多个DAC代码，在数据转换器中发生非线性。
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公开(公告)号：US09306777B2
公开(公告)日：2016-04-05
申请号：US14183513
申请日：2014-02-18
Inventor： Jung Woo Park , Young Jae Lee , Hyun Kyu Yu , Byung Hun Min , Seong Do Kim , Hoai Nam Nguyen , Sang Gug Lee
CPC classification number: H04L25/08 , H03D7/1441 , H03D7/1458 , H03H19/004
Abstract: A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.
Abstract translation: 直接转换接收机包括：高线性混频器装置，包括：采样单元，根据采样频率对输入电流进行采样;以及缓冲单元，其具有低输入阻抗，从采样器单元接收输出信号，放大接收信号 ，并输出电流信号; 以及滤波器装置对来自混频器装置的输出信号进行抽取，并对抽取的信号进行FIR滤波。
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公开(公告)号：US09209844B2
公开(公告)日：2015-12-08
申请号：US13737726
申请日：2013-01-09
Inventor： Seon-Ho Han , Hyun Kyu Yu
CPC classification number: H04B1/06 , H04B1/0014
Abstract: The inventive concept relates to a wireless communication receiver. The wireless communication receiver includes a second off-chip RF filter, an RF-to-digital converter and a digital pre-processor processing a signal converted into a digital. The RF-to-digital converter converts an RF signal being received into a digital signal of DC frequency band or intermediate frequency band and has a dynamic range that can process a wanted RF band signal and unwanted signals near to the wanted RF band signal. The digital pre-processor digitally controls a signal gain to transmit it to a modulator/demodulator.
Abstract translation: 本发明构思涉及无线通信接收机。 无线通信接收机包括第二片外RF滤波器，RF到数字转换器和处理转换成数字信号的数字预处理器。 RF-数字转换器将接收的RF信号转换为DC频带或中频带的数字信号，并且具有可处理所需RF频带信号的动态范围和靠近所需RF频带信号的不需要的信号。 数字预处理器以数字方式控制信号增益，将其发送到调制器/解调器。
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