公开(公告)号：US20130234766A1

公开(公告)日：2013-09-12

申请号：US13789691

申请日：2013-03-08

Applicant: ETRON TECHNOLOGY, INC.

Inventor： Yi-Hao Chang ,  Shih-Hsing Wang ,  Wen-Tung Yang ,  Yen-An Chang

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K19/0016

Abstract: An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal.

Abstract translation: 输入接收机包括第一输入接收单元，第二输入接收单元，延迟单元和第一逻辑单元。 第一输入接收单元接收反向唤醒信号，外部时钟使能信号，第一电压和参考信号，然后根据外部时钟使能信号和参考信号产生第一使能信号。 第二输入接收单元接收外部时钟使能信号，第一电压和反向使能电压，然后根据外部时钟使能信号产生第二使能信号作为其输出。 延迟单元根据第二使能信号产生唤醒信号。 第一逻辑单元接收唤醒信号和第一使能信号，然后根据唤醒信号和第一使能信号产生内部时钟使能信号。

公开(公告)号：US08773179B2

公开(公告)日：2014-07-08

申请号：US13789691

申请日：2013-03-08

Applicant: Etron Technology, Inc.

Inventor： Yi-Hao Chang ,  Shih-Hsing Wang ,  Wen-Tung Yang ,  Yen-An Chang

IPC: H03L7/00 ,  H03K19/00 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K19/0016

Abstract: An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal.

Abstract translation: 输入接收机包括第一输入接收单元，第二输入接收单元，延迟单元和第一逻辑单元。 第一输入接收单元接收反向唤醒信号，外部时钟使能信号，第一电压和参考信号，然后根据外部时钟使能信号和参考信号产生第一使能信号。 第二输入接收单元接收外部时钟使能信号，第一电压和反向使能电压，然后根据外部时钟使能信号产生第二使能信号作为其输出。 延迟单元根据第二使能信号产生唤醒信号。 第一逻辑单元接收唤醒信号和第一使能信号，然后根据唤醒信号和第一使能信号产生内部时钟使能信号。