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1.发明授权公开(公告)号：US12224768B2
公开(公告)日：2025-02-11
申请号：US18217892
申请日：2023-07-03
Applicant: ETRON TECHNOLOGY, INC.
Inventor： Ho-Yin Chen , Han-Hsien Wang , Han-Nung Yeh
Abstract: An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.
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公开(公告)号：US12159936B2
公开(公告)日：2024-12-03
申请号：US17394662
申请日：2021-08-05
Inventor： Chao-Chun Lu
IPC: H01L29/78 , H01L29/417 , H01L29/66
Abstract: A transistor structure includes a semiconductor substrate, a channel layer, a gate structure and a first conductive region. The semiconductor substrate includes a semiconductor surface. The channel layer is independent from the semiconductor substrate and covers the semiconductor surface. The gate structure, covers the channel layer. The first conductive region is coupled to the channel layer.
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公开(公告)号：US20240112707A1
公开(公告)日：2024-04-04
申请号：US18540888
申请日：2023-12-15
Applicant: Etron Technology, Inc
Inventor： Der-Min Yuan , Yen-An Chang , Wei-Ming Huang
IPC: G11C7/10 , G11C11/4074
CPC classification number: G11C7/1075 , G11C11/4074 , G06F12/0882
Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.
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公开(公告)号：US11869972B2
公开(公告)日：2024-01-09
申请号：US16388836
申请日：2019-04-18
Applicant: Etron Technology, Inc.
Inventor： Chao-Chun Lu
IPC: H01L29/78 , H01L29/10 , H01L29/08 , H01L29/06 , H01L29/66 , H01L21/762 , H01L21/02 , H01L29/417 , H01L29/40 , H01L21/3213 , H01L21/265 , H01L29/49 , H01L21/311
CPC classification number: H01L29/7851 , H01L21/0262 , H01L21/02532 , H01L21/02598 , H01L21/02636 , H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/401 , H01L29/41783 , H01L29/6656 , H01L29/66795 , H01L21/0228 , H01L21/26513 , H01L21/31111 , H01L21/32133 , H01L29/4933
Abstract: A transistor structure includes a gate structure, a channel region, a drain region and a source region. The gate structure is positioned above a silicon surface of a first silicon material, the channel region is under the silicon surface, and the channel region includes a first terminal and a second terminal. The drain/source region is independent and not derived from the first silicon material, the drain region includes a first predetermined physical boundary directly connected to the first terminal of the channel region, and the source region includes a second predetermined physical boundary directly connected to the second terminal of the channel region. The drain/source region includes a lower portion below the silicon surface and the bottom of the lower portion of the drain/source region is confined to an isolator, and sidewalls of the drain/source region are confined to spacers except sidewalls of the lower portion of the drain/source region.
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5.发明公开公开(公告)号：US20230387938A1
公开(公告)日：2023-11-30
申请号：US18217892
申请日：2023-07-03
Applicant: ETRON TECHNOLOGY, INC.
Inventor： Ho-Yin CHEN , Han-Hsien WANG , Han-Nung YEH
CPC classification number: H03M13/098 , H03M13/6597 , H03M13/1108
Abstract: An error correction method comprises; when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.
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Patent Agency Ranking
公开(公告)号：US11825645B2
公开(公告)日：2023-11-21
申请号：US17337391
申请日：2021-06-02
Applicant: Etron Technology, Inc.
Inventor： Chao-Chun Lu
IPC: H10B12/00
CPC classification number: H10B12/315 , H10B12/0335 , H10B12/053 , H10B12/34 , H10B12/482
Abstract: The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery.
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7.发明授权公开(公告)号：US11736121B1
公开(公告)日：2023-08-22
申请号：US17827029
申请日：2022-05-27
Applicant: ETRON TECHNOLOGY, INC.
Inventor： Ho-Yin Chen , Han-Hsien Wang , Han-Nung Yeh
CPC classification number: H03M13/098 , H03M13/1108 , H03M13/6597
Abstract: An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.
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公开(公告)号：US20230170330A1
公开(公告)日：2023-06-01
申请号：US18072283
申请日：2022-11-30
Applicant: ETRON TECHNOLOGY, INC.
Inventor： Chun SHIAH
IPC: H01L25/065
CPC classification number: H01L25/0657 , H01L2225/0651 , H01L2225/06513
Abstract: The invention provides a memory module, comprising a first memory die with a first surface and a third surface opposite to the first surface, wherein a first redistribution layer and a first original pad set are formed over the first surface; a second memory die with a second surface and a fourth surface opposite to the second surface, wherein a second original pad set are formed over the second surface; a wire bonding pad set disposed over the first surface, wherein the wire bonding pad set are electrically connected with the first original pad set; and a plurality of wires bonded to the wire bonding pad set, wherein the first memory die is bonded to the second memory die, the first surface faces the second surface, and the second original pad set are electrically connected with the wire bonding pad set.
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公开(公告)号：US20220415900A1
公开(公告)日：2022-12-29
申请号：US17894184
申请日：2022-08-24
Inventor： Chao-Chun Lu
IPC: H01L27/108 , G11C5/02 , H01L27/06 , H01L25/065
Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.
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公开(公告)号：US11456300B2
公开(公告)日：2022-09-27
申请号：US17189270
申请日：2021-03-02
Inventor： Chao-Chun Lu
IPC: G11C11/24 , H01L27/108 , G11C5/02 , H01L27/06 , H01L25/065
Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.
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